DAC Current-Source Weighting to Reduce Distortion Errors
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Solution Overview
Problem
Digital-to-analog converters (DACs) face performance issues due to mismatches in circuit components, leading to distortions such as rise/fall asymmetry, current amplitude mismatches, and timing offsets, which current technologies struggle to address effectively in terms of complexity, power consumption, and footprint.
Innovation Solution
The proposed DAC architecture minimizes statistical error metrics by optimizing the weights of current sources to reduce glitch errors, static errors, and timing offset errors, using differential evolution, simulated annealing, and digital pre-compensation techniques to achieve low distortion with fewer switches, thereby improving signal-to-noise distortion ratio (SNDR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional binary-weighted current sources are used in DAC, then the device complexity is low, but manufacturing precision deteriorates due to circuit component mismatches causing rise/fall asymmetry, amplitude mismatches, and timing offsets
Solution Approach 1:
The patent changes the weight parameters of current sources from traditional binary weights (powers of two) to optimized non-integer weights. This parameter modification allows the system to compensate for circuit component mismatches and reduce distortion errors while maintaining a manageable number of current sources, thereby improving manufacturing precision without significantly increasing device complexity.
Solution Approach 2:
The patent applies digital pre-compensation techniques that perform preliminary correction of expected distortion errors before the DAC conversion process. By pre-calculating and applying compensation values based on known circuit component characteristics, the system proactively counteracts anticipated mismatches and asymmetries, improving output accuracy without requiring additional physical circuit elements.
2Manufacturing precision
If segmented DAC architecture is used to reduce distortion errors, then manufacturing precision improves, but device complexity increases due to additional switches and circuit elements
Solution Approach 1:
Instead of increasing the number of switches through segmentation, the patent modifies the weight parameters of existing current sources to non-integer values. This approach achieves distortion error reduction by optimizing the mathematical relationships between current weights, thereby improving manufacturing precision without proportionally increasing device complexity.
Solution Approach 2:
The patent replaces the mechanical approach of adding more physical switches (segmentation) with a computational/mathematical approach using optimized weight parameters and digital pre-compensation. This substitution achieves similar or better distortion reduction performance while maintaining lower hardware complexity.
3Manufacturing precision
If optimized current source weights are used to minimize error metrics, then manufacturing precision improves, but use of energy increases due to additional computation and control circuitry
Solution Approach 1:
The patent performs error minimization calculations and weight optimization in advance during the design and fabrication process. By pre-determining the optimal non-integer weights based on expected circuit characteristics, the system avoids the need for complex real-time computation during operation, thereby improving manufacturing precision while keeping operational power consumption relatively low.
Solution Approach 2:
The optimized weight parameters are designed to inherently compensate for typical circuit mismatches and asymmetries. This self-compensating mechanism reduces the need for additional active control circuitry and real-time adjustment mechanisms, thereby achieving error minimization with reduced energy consumption.
Data Source
AI summary
A digital-to-analog converter (DAC) comprises circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2N−1, and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.