Solid-State Image Sensor Comparator for Stable Inversion Timing
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Solution Overview
Problem
In solid-state image sensors, the shared power supply for the comparator leads to variations in drain voltage when the pixel signal coincides with the reference signal, causing timing errors in comparison results, resulting in non-linearity and degradation of image quality during analog-digital conversion.
Innovation Solution
The implementation of a comparator configuration with specific transistor arrangements, including a first transistor with its gate connected to the reference signal and source connected to the pixel signal, and a second transistor with its gate connected to the drain of the first transistor, along with additional transistors for biasing and voltage regulation, to stabilize the drain-source voltage and improve timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the comparator shares the pixel circuit power supply to reduce power consumption, then power consumption is reduced, but the drain voltage of the pMOS transistor varies when the pixel signal coincides with the reference signal, causing inversion timing errors and degrading image quality
Solution Approach 1:
The power supply is segmented into two independent parts: one for the pixel circuit and another dedicated power supply for the comparator. This separation prevents the drain voltage of the pMOS transistor from varying due to pixel circuit operations, thereby eliminating inversion timing errors while maintaining reduced power consumption through the shared architecture.
Solution Approach 2:
A dedicated power supply acts as an intermediary between the pixel circuit and the comparator, providing stable voltage to the comparator's pMOS transistor. This intermediary power supply isolates the comparator from voltage variations caused by the pixel circuit, ensuring accurate inversion timing without requiring full power supply independence.
2Measurement precision
If a dedicated power supply is provided for the comparator to ensure stable drain voltage, then inversion timing accuracy is improved, but power consumption increases compared to shared power supply configuration
Solution Approach 1:
The power supply system is segmented to provide dedicated voltage regulation only for the comparator's critical pMOS transistor, while other comparator components can share power with the pixel circuit. This selective segmentation maintains inversion timing accuracy while minimizing the power overhead of a fully dedicated power supply.
3Device complexity
If the drain voltage of the pMOS transistor varies according to pixel signal level, then the comparator can operate with shared power supply, but the comparison result inversion timing shifts from ideal timing, causing non-linearity in digital signal
Solution Approach 1:
The power supply is segmented to isolate the comparator's pMOS transistor from pixel circuit voltage variations. This segmentation ensures that the drain voltage remains stable during comparison operations, preventing inversion timing shifts and maintaining AD conversion linearity while keeping the overall device complexity low through a simplified dual-power approach.
Solution Approach 2:
The power supply voltage parameter for the comparator is changed from being coupled to the pixel circuit power supply to being independently regulated. This parameter change stabilizes the drain voltage of the pMOS transistor, eliminating the non-linearity in AD conversion caused by voltage variations while maintaining a relatively simple power supply architecture.
Data Source
AI summary
A solid-state image sensor includes: an input transistor configured to output, from a drain, a drain voltage according to an input voltage input to a source in a case where the input voltage substantially coincides with a predetermined reference voltage input to a gate; and an output transistor configured to output a signal indicating whether or not a difference between the input voltage input to a source and the drain voltage input to a gate exceeds a predetermined threshold voltage as a comparison result between the input voltage and the reference voltage.