SAR ADC Clamping Stage for Accurate High-Impedance Decisions
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Solution Overview
Problem
Existing successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in achieving improved performance, particularly in terms of accuracy and efficiency during the conversion process.
Innovation Solution
The proposed solution involves an apparatus and control method for a SAR ADC that includes a high gain input stage, a clamping and filtering stage, and a decision-making stage. The clamping and filtering stage clamps a voltage on a high impedance node to a predetermined level approximately equal to a diode voltage drop, and the decision-making stage is connected to the output of the clamping and filtering stage to enhance the conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high gain input stage is used in SAR ADC, then conversion accuracy is improved, but circuit complexity increases
Solution Approach 1:
The amplifier is divided into multiple gain stages (first gain stage, second gain stage, third gain stage) with different gain values. Each stage processes the signal with a specific gain, allowing the system to achieve high overall gain while maintaining flexibility in design and reducing the complexity of any single stage.
Solution Approach 2:
The patent implements dynamic gain selection where the gain of each stage can be adjusted based on the input signal characteristics. The control circuit selectively activates different gain stages depending on the required conversion precision, allowing the system to adapt between high accuracy mode and lower complexity mode.
2Measurement precision
If multiple gain stages are implemented, then conversion precision is improved, but conversion speed decreases
Solution Approach 1:
The patent applies partial action by selectively enabling only the necessary number of gain stages based on the input signal requirements. For signals requiring high precision, all three gain stages are activated. For less critical conversions, fewer stages are used, thus maintaining conversion speed while achieving sufficient precision.
Solution Approach 2:
The control circuit periodically evaluates the input signal characteristics and dynamically adjusts the activation of gain stages between conversion cycles. This periodic adaptation allows the system to optimize between speed and precision for each conversion based on current signal conditions.
3Stability of the object's composition
If clamping and filtering stage is added to high impedance node, then signal stability is improved, but device complexity increases
Solution Approach 1:
The clamping and filtering stage acts as an intermediary between the high impedance node and the decision-making stage. It conditions the signal by clamping voltage to predetermined levels and filtering noise, providing a stable input to the decision-making stage without requiring complex modifications to the core ADC architecture.
Data Source
AI summary
An apparatus includes a high gain input stage configured as an integrator in a successive approximation register (SAR) analog-to-digital converter (ADC), a clamping and filtering stage configured to clamp a voltage on a high impedance node to a predetermined level approximately equal to a diode voltage drop in a clamping mode of an SAR cycle, and a decision-making stage connected to an output of the clamping and filtering stage.