Feedforward Noise-Shaping ADC for Fast High-Resolution Conversion
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) circuits face challenges in achieving high resolution within short conversion times while minimizing power consumption, as they often trade off resolution for speed or consume excessive power.
Innovation Solution
The implementation of a feedforward noise shaping loop with noise shaping capacitors allows for high-resolution analog-to-digital conversion in a short time duration, enabling low power consumption and reducing the need for high clock rates, while also supporting multiplexed input signals and dynamic range handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If integration time is increased to achieve higher resolution, then measurement precision is improved, but conversion speed deteriorates
Solution Approach 1:
The patent implements a noise shaping loop that feeds back quantization error information to the integrator input. This feedback mechanism shapes the quantization noise spectrum, pushing noise to higher frequencies where it can be filtered out, thereby improving effective resolution without requiring longer integration times.
Solution Approach 2:
The patent changes the temporal distribution of quantization error through noise shaping, concentrating error energy in specific frequency bands. This allows the system to achieve higher effective resolution by filtering shaped noise rather than increasing integration time, thus maintaining fast conversion speed.
2Measurement precision
If integration time is increased to achieve higher resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The noise shaping feedback loop enables the system to achieve higher effective resolution through spectral shaping rather than extended integration. This reduces the time components must remain active, thereby lowering power consumption while maintaining high resolution.
Solution Approach 2:
The patent uses periodic switching of the integrator between integration and discharge phases, with the noise shaping loop operating in synchrony. This periodic operation allows for shorter duty cycles compared to continuous long-duration integration, reducing average power consumption while achieving high resolution through noise shaping.
3Speed
If clock rate is increased to achieve faster conversion, then conversion speed is improved, but power consumption increases
Solution Approach 1:
The noise shaping feedback mechanism allows the ADC to achieve high conversion speeds without proportionally increasing clock rate. By shaping quantization noise in the frequency domain, the system can use lower clock rates while maintaining high effective resolution and fast conversion performance.
4Measurement precision
If noise shaping loop is added to improve resolution and speed, then measurement precision and conversion speed are improved, but device complexity increases
Solution Approach 1:
The patent combines the noise shaping feedback path with the existing dual-slope ADC architecture, merging the integrator, comparator, and noise shaping capacitors into a unified circuit. This integration reduces overall complexity compared to implementing noise shaping as a separate post-processing stage.
Solution Approach 2:
The integrator serves multiple functions: it performs the primary integration of the input signal, accumulates quantization error for noise shaping, and can be discharged to reset the integration cycle. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity.
Data Source
AI summary
An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.


