Time-Interleaved ADC Pseudo-Periodic Estimation for Spur Suppression
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Solution Overview
Problem
High sampling rate analog-to-digital converters (ADCs) with time-interleaved architectures face issues due to direct current (DC) offset and time interleaving mismatches between sub-ADCs, which conventional compensation schemes fail to optimally address, leading to suboptimal performance.
Innovation Solution
A randomly interspersed pseudo periodic (RIPP) ADC operates in three phases: a transition phase for settling, an estimation phase for periodic IL mismatch estimation, and a randomization phase to randomize the sampling clock phases among sub-ADCs, ensuring each sub-ADC experiences all phases, allowing for effective estimation and correction of DC offset and IL mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional compensation schemes are used for time-interleaved ADCs, then DC offset and IL mismatch compensation is provided, but residual IL spurs remain at levels above the noise floor, leading to suboptimal performance
Solution Approach 1:
The patent implements periodic IL estimation phases interspersed within the normal operation of the time-interleaved ADC. During these periodic phases, the sampling clock phases are randomized and then restored, allowing for fresh IL mismatch estimation that continuously updates compensation parameters, thereby reducing residual IL spurs to or below the noise floor
Solution Approach 2:
The patent dynamically changes the sampling clock phase parameters by randomizing them during estimation phases. This parameter change allows the system to capture IL mismatch under varying phase conditions, improving the accuracy of mismatch estimation and subsequent compensation, which eliminates residual spurs that conventional fixed-parameter schemes cannot address
2Speed
If time-interleaved architecture with multiple sub-ADCs is used to achieve high sampling rates, then sampling rate is increased, but DC offset and time interleaving mismatches between sub-ADCs occur
Solution Approach 1:
The patent implements a feedback mechanism where IL mismatch is continuously estimated during periodic estimation phases and used to update compensation parameters. This closed-loop feedback allows the system to detect and correct mismatches between sub-ADCs, maintaining signal accuracy despite the complexity of the time-interleaved architecture
Solution Approach 2:
The patent performs preliminary IL mismatch estimation and DC offset compensation before final signal processing. By estimating mismatches during dedicated estimation phases and pre-computing compensation parameters, the system prepares correction data in advance, ensuring accurate compensation is applied to maintain reliability at high sampling rates
Data Source
AI summary
Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.