Multi-ADC Timing Control for On-Die Noise-Aware Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microcontrollers with multiple analog-to-digital converters (ADCs) on a single chip face performance degradation when multiple ADCs operate simultaneously, leading to reduced precision and increased noise, which is not effectively addressed by current solutions that increase manufacturing costs and product size.
Innovation Solution
An integrated circuit (IC) with a first and second ADC disposed on a single semiconductor die, along with logic circuitry that marks digital values obtained during overlapping sampling periods as noisy, allowing for independent operation of multiple ADCs without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ADCs are placed on separate semiconductor dies, then manufacturing costs and product size increase, but ADC performance degradation is avoided
Solution Approach 1:
The patent segments the ADC operation into distinct phases (sampling phase and conversion phase) and assigns different priority levels to each phase. The sampling phase is given high priority to ensure noise-free sampling, while the conversion phase is given lower priority. This temporal segmentation allows multiple ADCs to share the same semiconductor die without mutual interference, as each ADC operates in its own time window for the critical sampling operation.
2Ease of manufacture
If multiple ADCs operate simultaneously on a single chip, then manufacturing cost and product size are reduced, but ADC precision degrades due to noise
Solution Approach 1:
The patent implements periodic action by cycling through multiple ADCs in a predetermined sequence, where each ADC is activated for its sampling phase in turn. This periodic activation ensures that only one ADC performs sampling at any given time, preventing noise interference from other ADCs. The conversion phase operates continuously or in parallel, but the critical sampling operation is periodic and isolated to maintain precision.
3Area of stationary object
If multiple ADCs share a single semiconductor die, then product size is reduced, but noise interference occurs during overlapping sampling periods
Solution Approach 1:
The patent introduces an intermediary control mechanism (the controller or logic circuit) that mediates between multiple ADCs sharing the same die. This intermediary manages the timing and activation of each ADC, ensuring that sampling operations are staggered and do not overlap. By acting as a mediator, the control logic prevents noise interference while allowing multiple ADCs to coexist on a single semiconductor die, thus reducing product size without sacrificing performance.
Data Source
AI summary
Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.