Under-Sampled SAR ADC with Matched Paths for Linearity

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Solution Overview

Problem

Under-sampled successive approximation register (SAR) analog to digital converters (ADCs) face challenges in achieving high bandwidth while minimizing nonlinearity issues, particularly due to the pedestal effect and other distortions, which require complex compensation circuits and calibration schemes, increasing design complexity and power consumption.

Innovation Solution

The implementation of a high bandwidth under-sampled SAR ADC with matched signal paths for the input and reference signals, utilizing a dual clock structure with a controllable phase offset and an asymmetrical driver to minimize drift and nonlinearity, allowing for resampling at each step and canceling out common distortions through signal subtraction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If under-sampled SAR ADC is used to achieve high bandwidth operation, then bandwidth is improved, but nonlinearity and distortions like pedestal effect increase

Engineering Contradiction:

ImprovebandwidthVSAvoidlinearity

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

The patent converts the harmful pedestal effect and nonlinearity into a beneficial common-mode signal that can be rejected. By intentionally allowing both the input signal path and reference signal path to experience the same nonlinearities and distortions, these effects become correlated and can be eliminated through differential subtraction in the comparator, thus converting harm into benefit

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent employs asymmetrical drivers with different drive strengths for the input signal path and reference signal path. This asymmetry is deliberately designed to compensate for systematic nonlinearities and achieve better linearity performance, as the different drive characteristics help balance out the pedestal effect and other distortions

Inventive Principle:

Principle #4Asymmetry

2Measurement precision

If complex compensation circuits and calibration schemes are added to reduce nonlinearity, then linearity is improved, but device complexity increases

Engineering Contradiction:

ImprovelinearityVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Instead of adding complex compensation circuits to fight against nonlinearity, the patent lets the nonlinearity exist in both paths and converts it into a common-mode signal that is naturally rejected by the differential comparator architecture, thereby improving linearity without increasing circuit complexity

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The matched signal paths serve multiple functions: they provide the necessary signal routing for ADC operation while simultaneously acting as distortion cancellation mechanisms. The same physical paths that carry the signals also generate the correlated distortions that will be rejected, eliminating the need for separate compensation circuits

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Measurement precision

If complex compensation circuits and calibration schemes are added to reduce nonlinearity, then linearity is improved, but power consumption increases

Engineering Contradiction:

ImprovelinearityVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent eliminates the need for power-hungry compensation circuits and calibration schemes by converting nonlinearity into a rejectable common-mode signal. The only additional power consumption comes from the asymmetrical drivers, which are more efficient than complex compensation circuits would be

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

4Measurement precision

If matched signal paths are used for input and reference signals, then nonlinearity is reduced, but thermal noise increases

Engineering Contradiction:

ImprovelinearityVSAvoidthermal noise

Core Design Contradiction:

Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent optimizes the electrical parameters of the matched signal paths, including resistance, capacitance, and drive strength, to achieve the right balance between distortion cancellation and noise performance. By carefully tuning these parameters, the system minimizes thermal noise while maintaining the distortion-rejection benefits of matched paths

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11502695B2High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization

Publication Date: 2022.11.15 CIENA CORP

AI summary

Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.