SAR ADC Comparator Alternation With Uneven Redundancy Allocation
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Solution Overview
Problem
Successive Approximation Register (SAR) type Analog-to-Digital Converters (ADCs) face limitations in speed due to the need for multiple clock cycles and comparator reset time, which can be bottlenecked by comparator offset mismatch and kickback noise, especially as resolution increases, requiring complex calibration and increased power consumption.
Innovation Solution
Alternating between sets of comparators with different precision and noise characteristics, allocating redundancy unevenly to compensate for lower accuracy in early decision cycles and using higher precision comparators for later cycles, thereby removing the comparator reset time from the critical path and optimizing redundancy allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a SAR ADC uses multiple clock cycles and comparator reset time for each bit decision, then measurement precision is improved, but speed deteriorates
Solution Approach 1:
The patent applies preliminary action by performing redundancy allocation in advance based on predicted comparator error patterns. The system pre-determines which comparators will be used in each decision cycle and allocates redundancy bits accordingly, allowing the ADC to operate faster without sacrificing accuracy. This eliminates the need for conservative reset timing while maintaining conversion precision.
Solution Approach 2:
The patent implements dynamics by making the redundancy allocation dynamic rather than static. The system adapts the amount of redundancy allocated to each decision cycle based on the specific comparator being used and its known error characteristics. This dynamic allocation allows the ADC to optimize the trade-off between speed and precision for each individual comparison operation.
2Productivity
If comparator reset time is reduced to increase speed, then productivity is improved, but measurement precision deteriorates due to offset mismatch and kickback noise
Solution Approach 1:
The patent applies preliminary action by pre-characterizing each comparator's offset mismatch and kickback noise properties before conversion operations. This pre-characterization data is stored and used to dynamically allocate redundancy bits for each decision cycle, allowing the system to compensate for known comparator imperfections without requiring lengthy reset periods. This enables faster operation while maintaining precision through software-based compensation rather than hardware-based reset timing.
Solution Approach 2:
The patent implements feedback by using the pre-measured comparator error characteristics to adjust redundancy allocation in real-time. The system continuously references the stored comparator performance data and adapts the conversion process accordingly, feeding back this information to optimize each decision cycle's precision requirements based on the specific comparator being used.
3Device complexity
If uniform redundancy allocation is used across all decision cycles, then device complexity is reduced, but measurement precision deteriorates due to comparator error accumulation
Solution Approach 1:
The patent applies local quality by making the redundancy allocation non-uniform and specific to each decision cycle and comparator. Instead of applying the same redundancy level everywhere, the system tailors the redundancy allocation to the local characteristics of each comparator and its associated error patterns. This localized approach maintains precision by addressing each comparator's specific weaknesses while keeping the overall system manageable through pre-computed allocation tables.
4Measurement precision
If calibration is performed to reduce offset mismatch, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies preliminary action by performing comprehensive comparator characterization during the manufacturing or initialization phase, storing the measured offset mismatch and kickback noise properties in memory. This pre-characterization replaces the need for complex real-time calibration circuits, as the error data is captured once and then used to dynamically allocate redundancy bits during normal operation. This approach maintains precision while dramatically reducing device complexity and power consumption compared to continuous calibration schemes.
Data Source
AI summary
A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.