ADC Receiver Echo Cancellation With Clock Phase Retuning
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Solution Overview
Problem
In full-duplex Ethernet systems, impedance mismatches cause echo signals with high-frequency components to be reflected back, leading to aliasing and reduced effective bandwidth, which existing methods attempt to mitigate by small phase adjustments of the clock signal, increasing the cost of phase selectors.
Innovation Solution
A receiver with an ADC, echo-cancellation circuit, and control circuit that allows for larger phase adjustments of the clock signal (1/128 of its period) by calculating updated tap coefficients for the echo-cancellation circuit, enabling effective echo cancellation without degrading signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If small phase adjustment of clock signal is used to avoid affecting received signal quality, then signal quality is maintained, but the cost of phase selector in analog circuits significantly increases
Solution Approach 1:
The patent replaces the mechanical/analog phase selector with a digital signal processing approach. Instead of using an expensive analog phase selector to make small phase adjustments, the invention uses a digital echo cancellation circuit that can handle larger phase adjustments (1/128 of clock period) by calculating updated tap coefficients, thereby substituting complex analog hardware with a more cost-effective digital processing method
Solution Approach 2:
The patent changes the phase adjustment parameter from small increments (1/1024 of clock period) to larger increments (1/128 of clock period). This parameter change allows the use of a simpler, lower-cost phase selector while maintaining effective echo cancellation through adaptive tap coefficient calculation in the digital domain
2Device complexity
If larger phase adjustment of clock signal is used, then the cost of phase selector is reduced, but the quality of received signal is affected
Solution Approach 1:
The patent replaces the mechanical/analog phase selector with a digital signal processing approach. Instead of using an expensive analog phase selector to make small phase adjustments, the invention uses a digital echo cancellation circuit that can handle larger phase adjustments (1/128 of clock period) by calculating updated tap coefficients, thereby substituting complex analog hardware with a more cost-effective digital processing method
Solution Approach 2:
The patent employs feedback through adaptive echo cancellation. When the clock phase is adjusted to a larger increment, the system calculates updated tap coefficients based on the new phase information and feeds this back to the echo cancellation circuit, allowing the system to adapt and maintain signal quality despite the larger phase adjustment
Data Source
AI summary
The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.