Time-Interleaved ADC Skew Estimation for Accurate Phase Convergence
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) devices face inaccuracies in timing error calibration, leading to incorrect convergence of phase errors between channels, affecting resolution and linearity.
Innovation Solution
A time-interleaved ADC device with a calibration circuit and a skew adjusting circuit that includes an estimating circuit, a feedback circuit, and an adjusting circuit to analyze time difference information of clock signals, generate detection signals, and output adjustment signals to reduce clock skew, ensuring accurate phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prior art calibration methods are used for timing error, then calibration can be performed, but the calibration accuracy is insufficient leading to incorrect phase error convergence
Solution Approach 1:
The patent implements a feedback mechanism where the calibration result is fed back to adjust the calibration process. The system performs initial calibration, evaluates the phase error convergence, and uses this information to refine subsequent calibration iterations, thereby improving both calibration accuracy and phase error convergence reliability
Solution Approach 2:
The patent applies preliminary calibration operations before the main conversion process to pre-adjust timing errors. By performing preliminary calibration actions on the clock signals and ADC circuits, the system establishes a more accurate baseline for subsequent operations, improving overall calibration precision
2Productivity
If multiple ADC circuits operate in parallel, then conversion speed increases, but clock skew between channels increases affecting resolution and linearity
Solution Approach 1:
The patent dynamically adjusts clock signal parameters (phase, timing) for each ADC circuit based on measured skew. By changing these temporal parameters individually for each channel, the system maintains parallel operation speed while compensating for skew-induced precision losses, thereby preserving both productivity and manufacturing precision
3Adaptability or versatility
If clock signals are distributed to multiple ADC circuits, then parallel processing capability increases, but clock skew between channels occurs
Solution Approach 1:
The patent segments the clock distribution system into individual adjustable channels, where each ADC circuit receives its own clock signal that can be independently calibrated. This segmentation allows parallel processing to proceed while enabling precise individual phase alignment adjustment for each channel, maintaining both adaptability and measurement precision
Data Source
AI summary
An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.