Localized Frequency-Multiplying DAC Cells for Lower Clock Power
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Solution Overview
Problem
Current digital-to-analog converters (DACs) require high clock signal frequencies, leading to increased power consumption and complexity in electronic devices, which can be mitigated by implementing frequency multiplication circuitry within the DAC cells to generate higher frequency analog signals without the need for additional amplification or filtering stages.
Innovation Solution
Incorporating frequency multiplication circuitry within each cell of the DAC, which receives a local oscillator signal and a bitstream, and outputs a multiplied gated LO signal with a higher frequency, allowing the DAC to generate unit power analog signals at frequencies double or quadruple the input frequency, thereby reducing the operating frequency of the local oscillator and digital front-end components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high clock signal frequencies are used in current DACs, then higher frequency analog signals can be generated, but power consumption increases and device complexity increases
Solution Approach 1:
The frequency multiplication function is segmented and distributed to individual DAC cells rather than using a centralized high-frequency clock distribution system. Each cell contains its own frequency multiplication circuitry that operates on a lower-frequency clock signal, dividing the frequency multiplication task across multiple independent units.
Solution Approach 2:
Frequency multiplication circuitry acts as an intermediary within each cell, converting the lower-frequency clock signal into higher-frequency drive signals for the switching elements. This intermediary mechanism eliminates the need for direct high-frequency clock distribution throughout the DAC architecture.
2Speed
If high clock signal frequencies are used in current DACs, then higher frequency analog signals can be generated, but device complexity increases
Solution Approach 1:
The DAC is divided into multiple independent cells, each with integrated frequency multiplication circuitry. This segmentation allows each cell to operate autonomously at lower frequencies while collectively achieving high-frequency output capability, simplifying the overall clock distribution architecture.
Solution Approach 2:
The frequency multiplication function is merged directly into each DAC cell, combining the clock generation and signal conversion functions at the cellular level. This integration eliminates the need for separate high-frequency clock distribution networks and external frequency multipliers.
3Use of energy by stationary object
If frequency multiplication circuitry is added to each cell, then operating frequency of the local oscillator can be reduced, but cell complexity increases
Solution Approach 1:
The operating parameters of each cell are changed to accept lower-frequency clock inputs, with the frequency multiplication circuitry compensating to achieve the required output frequencies. This parameter transformation allows the local oscillator to operate at reduced frequencies while maintaining overall system performance.
Data Source
AI summary
The current disclosure is related to digital-to-analog converters (DACs) with localized frequency multiplication circuits. For example, an electronic device may include a local oscillator (LO) providing clock signals, a digital front-end providing digital signals, a DAC, (e.g., a radio frequency DAC (RFDAC)), and one or more antennas. The DAC may include a number of cells (e.g., unit power amplifiers). Moreover, each cell may provide a unit power analog signal upon activation with a higher frequency than the received digital signals and clock signals. The DAC may provide an output signal (e.g., an analog signal) based on combining (e.g., aggregating) the unit power analog signals of the activated cells for transmission by the one or more antennas.