TIADC Sampling Clock Phase Randomization for Skew Tone Suppression

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Solution Overview

Problem

Conventional time interleaved analog-to-digital converters (TIADCs) suffer from residual skew tones due to phase errors in sampling clocks, which degrade their performance despite correction attempts.

Innovation Solution

A TIADC system that includes multiple ADCs, a control circuit, and a clock generation circuit, where the control circuit generates random or pseudo-random control values to adjust the phases of the sampling clocks, ensuring they are not fixed, thereby reducing or suppressing skew tones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional filtering methods are used to correct phase errors in TIADC, then phase error correction is achieved, but residual skew tones remain and performance degrades

Engineering Contradiction:
Improvephase error correctionVSAvoidskew tone suppression
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies dynamics by making the sampling clock phases variable rather than fixed. The control circuit dynamically adjusts the phase of each sub-ADC's sampling clock based on randomly generated control values, transforming the static phase correction approach into a dynamic one that prevents residual skew tones from persisting at fixed frequencies.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the phase parameter of the sampling clocks from fixed corrected values to randomly variable values. By periodically generating new random control values that adjust the clock phases, the system changes the operating parameters to eliminate the persistence of skew tones that occur with conventional fixed-phase correction methods.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If fixed phase correction is applied to sub-ADC sampling clocks, then initial phase errors are reduced, but residual skew tones are generated at fixed frequencies

Engineering Contradiction:
Improvesampling clock phase accuracyVSAvoidskew tones
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent transforms the static phase correction into a dynamic system where the control circuit continuously generates random control values to adjust the sampling clock phases. This dynamic adjustment prevents the system from settling into fixed-frequency skew tones while maintaining phase accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent converts the harmful fixed-frequency skew tones into beneficial random-phase operation. By introducing random phase variations through dynamically generated control values, the system transforms the deterministic harmful skew tones into stochastic behavior that averages out and eliminates the harmful frequency components.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Productivity

If multiple sub-ADCs operate with fixed phase differences, then time interleaving function is achieved, but phase mismatches cause performance degradation

Engineering Contradiction:
Improvesampling rate multiplicationVSAvoidphase difference accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent maintains the time interleaving function by keeping multiple sub-ADCs operating with different phases, but makes the phase differences dynamic rather than fixed. The control circuit generates random control values that continuously adjust the phases, allowing the system to maintain productivity while improving measurement precision through dynamic phase management.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the phase difference parameter from fixed values (e.g., exactly 90 degrees) to randomly variable values around the ideal phases. This parameter change allows the system to maintain the time interleaving functionality while eliminating the precision losses caused by fixed phase mismatches.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11451235B2Time interleaved analog-to-digital converter
Publication Date: 2022.09.20 REALTEK SEMICON CORP
  • US11451235B2 patent drawing
  • US11451235B2 patent drawing
  • US11451235B2 patent drawing

AI summary

A time interleaved analog-to-digital converter (TIADC) is provided. The TIADC converts an input signal into a digital output signal and includes N analog-to-digital converters (ADCs), a clock generation circuit, and a control circuit. The N ADCs receive the input signal and sample the input signal according to N sampling clocks to each generate a digital output code, N being an integer greater than or equal to 2. The clock generation circuit is configured to receive a working clock and a set of control values and to generate the N sampling clocks according to the set of control values and the working clock. The control circuit is configured to periodically generate the set of control values based on a pseudo random number and to output the digital output codes in turn as the digital output signal.