On-Chip ADC Linearity Testing With a Moving Histogram
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Solution Overview
Problem
Existing ADC linearity testing methods, such as the all-code histogram based method, require significant computational resources and time due to the need for large memory storage and extensive data transfer, making them inefficient for production testing, especially when implemented on low-cost or low-performance microcontrollers.
Innovation Solution
A moving histogram based method is introduced, which dynamically computes DNL and INL values using a small fixed number of bins, sliding across the ADC output code range, reducing computational complexity and memory requirements, allowing for on-chip ADC linearity testing on low-cost microcontrollers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all-code histogram based method is used for ADC linearity testing, then measurement precision is improved, but productivity deteriorates due to significant test time requirements
Solution Approach 1:
The patent divides the full ADC code range into multiple segments or windows. Instead of processing all codes simultaneously, the histogram is computed for a limited window of codes at a time, then shifted to process adjacent code ranges. This segmentation reduces the computational burden per processing cycle while maintaining comprehensive coverage of the entire ADC transfer function for accurate DNL and INL measurements.
Solution Approach 2:
The patent employs a dynamic sliding window approach where the histogram processing window moves across the ADC code range. The window position is dynamically adjusted to process different code segments sequentially. This dynamic approach allows the system to maintain a small, fixed-size histogram buffer while still evaluating linearity parameters across the full code range, significantly reducing memory requirements and processing time compared to static all-code processing.
2Measurement precision
If all-code histogram based method is used for ADC linearity testing, then measurement precision is improved, but device complexity increases due to large memory storage requirements
Solution Approach 1:
The patent segments the ADC code range into smaller windows, allowing the histogram to store counts for only a limited number of codes at a time rather than all possible codes. This segmentation enables the use of small, fixed-size memory buffers while still achieving comprehensive linearity assessment through multiple sequential measurements across different code ranges.
Solution Approach 2:
The sliding window mechanism dynamically repositions the histogram buffer across different code ranges. By moving the window through the full code space and accumulating results, the system achieves complete linearity characterization using minimal memory. The dynamic approach allows reuse of the same small buffer for different code segments, eliminating the need for large static storage.
3Measurement precision
If all-code histogram based method is used for ADC linearity testing, then measurement precision is improved, but loss of time increases due to extensive data transfer
Solution Approach 1:
The patent processes ADC codes in segmented windows rather than transferring and processing all codes at once. Each window contains a manageable subset of codes that can be processed locally with minimal data transfer. This segmentation reduces the volume of data that needs to be transferred between the ADC, processor, and memory, thereby reducing data transfer time while maintaining measurement accuracy through comprehensive coverage of all code ranges.
Solution Approach 2:
The dynamic sliding window approach enables incremental processing of code ranges. Instead of requiring complete data collection and transfer before processing, the system can dynamically shift the processing window and begin computations on each segment as data becomes available. This reduces the peak data transfer requirements and allows overlapping of data acquisition with processing operations, minimizing total test time.
Data Source
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AI summary
In described examples, a method of testing linearity of an ADC includes receiving (1310) a trigger signal indicating an ADC input voltage step adjustment, and reading (1311) an ADC output sample upon receiving the trigger signal. The ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes. Also, the method includes computing (1312) a histogram of code occurrences for M consecutive ADC output codes. The histogram includes M number of bins corresponding to the M consecutive ADC output codes, where M is less than N. Further, the method includes updating a DNL value and an INL value according to the histogram at an interval of K number of ADC output sample readings, and shifting (1330) the histogram by one ADC output code after updating the DNL and the INL values.