Analogue-Digital Converters TRIZ Cases

Time-domain interpolation comparators enable direct RF sampling at high speed while cutting mixer hardware, power use, and timing drift.

On-chip averaging and comparison of interleaved ADC outputs cuts clock skew calibration power and time, even above Nyquist frequency.

Carrier-based input scaling prevents ADC overload and cuts 1/f noise by restoring gain digitally for wider dynamic range.

Small multi-level dither and output correlation calibrate pipelined ADC stages, reducing inter-stage gain error and non-linearity.

Burst sampling uses impulse duty-cycle patterns to cut ADC power and chip area while preserving high-speed signal conversion performance.

Correlator- and LMS-based calibration corrects random chopper gain and offset errors to lower noise floor in data converters.

Charge balancing with asynchronous and fractional time counts improves low-light photocurrent measurement accuracy and dynamic range.

Embedded code words and radar data share one serial link, cutting sync wiring, power use, and timing errors between front end and baseband.

A coupling correction circuit applies in-phase and quadrature-phase clock adjustments to suppress crosstalk and multiplicative jitter in ADC transceivers.

A split interconnect architecture routes packetized memory traffic through a NoC to cut programmable fabric bottlenecks and latency.

A resonant circuit and passive distortion signal improve multi-inductor measurement resolution beyond ADC bit limits with low circuit complexity.

A folded current mirror sampler separates input matching from load gain, improving bandwidth, S11 performance, and current scaling.

Random pulse injection and correlation-based calibration correct gain, timing, and bandwidth mismatch in interleaved ADC channels.

Varying ADC bias and sampling points averages out INL error, improving fast laser distance measurements in trackers and scanners.

Randomized ADC channel selection cuts chip wiring while reducing mismatch spur in time-interleaved digital output signals.

Dynamic bias and gain control prevents microphone clamping and sound cracks, keeping recordings clear under loud input.

Three test modes separate ADC and signal-chain noise, enabling single-insertion SNR and INL measurement with lower test time and cost.

FFT harmonic phase and amplitude analysis speeds ADC INL measurement while correcting phase distortion and avoiding architecture-dependent methods.

A current-steering first stage and cascaded SAR residue path raise ADC speed and SNR while cutting power and gain-bandwidth demands.

Built-in sequence control tests ADC multiplexer channels for shorts and coupling, cutting microcontroller wait time in safety-critical use.

Sub-sample trigger binning, filtering, and decimation reduce asynchronous sampling distortion while improving real-time waveform SNR.

A sliding histogram computes DNL and INL across ADC codes with far less memory and test time, enabling on-chip linearity testing.

Shifted encode values and differential sampling prevent integrated step errors in high-speed A/D conversion while preserving accuracy.

A shared time-to-digital converter handles both ADC and DAC modes to cut silicon area and reduce conversion mismatch.

Color-coded ternary patterns with one-digit changes cut code length and reading errors in compact optical length measurement.

Dynamic filter bandwidth and signal selection improve ADC signal-to-noise ratio while preserving low-frequency data signals.

On-chip max-value averaging and phase comparison reduce clock skew in time-interleaved ADCs without extra ADC circuits or off-chip calibration.

Split FMCW radar receive paths filter low beat frequencies and boost higher ones to improve distant object detection under noise.

Fast FIR filtering with pre- and post-transformers corrects interleaved ADC response mismatch while cutting multiplier count for real-time equalization.

Variable cycle periods in a cyclic ADC cut conversion time and power while limiting error amplification at high resolution.

Early MSB integration lets synaptic arrays start pulse processing before ADC finishes, cutting integration delay and ADC timing overhead.

Grouping sensor data with different sampling rates into one series removes duplicate timing data and improves compression efficiency.

Correlator and LMS calibration removes random chopper offset and gain errors, cutting noise floor degradation in interleaved ADCs.

Using resonant-circuit oscillation as built-in dithering, this case improves inductive distance or position sensing without higher-bit ADCs.

Comparator-driven supply tuning balances skew between interleaved ADC channels to improve digital output accuracy, SFDR, SNR, and ENOB.

Continuous max-min monitoring calibrates offset, gain, and timing skew in time-interleaved ADCs with low silicon and power overhead.

Time-shared A/D conversion lets sine and cosine resolver signals share the same converter errors, improving quadrature accuracy and position measurement.

Alignment signals synchronize parallel ADC channels and clock timing to cut combined output noise in high-speed conversion.

Embedded valid-data codes in a radar front-end serial stream cut sync wiring, power use, and interface complexity while preserving timing accuracy.

An on-chip charge pump creates the negative rail for ADC input buffering while synchronized clock ratios place pump noise in the filter rejection band.

Separate ground traces let the decoder feed the MDAC with a stable reference, reducing pipelined ADC area and improving accuracy.

A two-stage SAR ADC uses more voltage generators for MSBs and fewer for LSBs to speed conversion while cutting power and circuit area.

Independent event and ready-signal control lets multiple ADCs sample simultaneously without heavy host-side synchronization overhead.

Dual sample-and-hold paths let a pipelined ADC store, amplify, and convert in parallel to cut conversion time and raise throughput.

Dither-based background calibration corrects DAC, reference, and quantization nonlinearity in multi-step ADCs while reducing power use and test time.

Redundant ADC signal paths expose phase drift and enable compensation, improving phase difference accuracy in Coriolis mass flowmeters.

A PRBS-driven stochastic comparator estimates and corrects pipeline ADC gain and memory errors, improving accuracy with lower amplifier power.

Voltage-divider ID wiring lets exchangeable circuit units self-identify on an internal bus, avoiding manual addressing and extra hardware.

Multiple analog channels preprocess wide-range signals with amplification, attenuation, filtering, and self-correction to improve A/D accuracy.

Phase error detectors iteratively align interleaved ADC sampling phases to correct timing skew, improving conversion accuracy and power efficiency.