Interleaved ADC Phase Calibration for Sampling Skew Correction
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Solution Overview
Problem
In high-speed data transmission systems, time-interleaved analog to digital converter (ADC) receiver solutions face accuracy issues due to imperfections in the sampling phases of interleaved ADC channels, which affect the conversion rate and power consumption.
Innovation Solution
A phase control circuit is implemented to adjust the sampling phases of multiple time-interleaved ADCs by using phase error detectors to calculate and refine phase delay settings, ensuring accurate phase alignment and reducing phase errors through iterative calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple time-interleaved ADC channels are used to increase conversion rate and reduce power, then productivity and energy efficiency are improved, but measurement precision deteriorates due to phase imperfections
Solution Approach 1:
The patent implements a feedback mechanism where phase error detectors continuously monitor the phase alignment of multiple ADC channels and feed back correction signals to adjust the sampling phases. This closed-loop control system dynamically compensates for phase imperfections, maintaining measurement precision while utilizing multiple interleaved channels for high conversion rates.
Solution Approach 2:
The patent adjusts the sampling phase parameters of individual ADC channels dynamically based on detected phase errors. By changing the phase parameter of each channel's sampling clock, the system compensates for timing skew and aligns all channels, thereby maintaining precision despite using multiple parallel converters for increased productivity.
2Measurement precision
If phase error detection and correction circuits are added to improve sampling phase accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the phase correction function into separate modular components: phase error detectors for each ADC channel and individual phase adjusters. This segmentation allows each component to perform a specific function independently, making the overall complex system manageable and enabling targeted optimization of each module without affecting the entire system.
Solution Approach 2:
The patent introduces phase error detectors as intermediary components that bridge the gap between the ADC channels and the control system. These detectors act as mediators that convert phase timing differences into measurable error signals, which then guide the phase adjustment process, simplifying the control mechanism while maintaining precision.
Data Source
AI summary
An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.