Pipelined ADC Ground Routing for Stable Reference Voltage
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Solution Overview
Problem
Conventional pipelined ADCs face limitations in design flexibility and circuit area due to the constraints on reference voltage generation, which affects the stability and accuracy of the conversion process.
Innovation Solution
The pipelined ADC design includes a sub-ADC, MDAC, and decoder, where the decoder provides the MDAC with a ground signal, using metal traces to connect the sub-ADC and decoder to separate ground pads, stabilizing the reference voltage and reducing circuit area by eliminating the need for unit gain buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional reference voltage generation circuits are used with unit gain buffers, then the reference voltage can be provided, but the circuit area becomes large
Solution Approach 1:
The patent extracts and eliminates the unit gain buffer component from the reference voltage generation circuit. By directly connecting the reference voltage generation circuit to the MDAC through separate metal traces, the unnecessary buffering stage is removed, significantly reducing circuit area while maintaining reference voltage stability through direct low-impedance connections.
Solution Approach 2:
The patent segments the ground connections by providing separate ground paths for the reference voltage generation circuit and the MDAC. This segmentation prevents ground noise coupling between these sensitive circuits, ensuring reference voltage stability without requiring additional buffering components that would increase area.
2Adaptability or versatility
If strict constraints are imposed on reference voltage values (VREF+=0.75VDD, VREF−=0.25VDD), then stable operation is ensured, but design flexibility is reduced
Solution Approach 1:
The patent introduces adjustable resistors (R1 and R2) in the reference voltage generation circuit, enabling dynamic adjustment of VREF+ and VREF− values. This allows the reference voltages to be optimized for different operating conditions and input signal ranges, providing design flexibility while maintaining operation stability through proper biasing and voltage division.
3Reliability
If unit gain buffers are added to stabilize reference voltage, then operation stability improves, but circuit area increases
Solution Approach 1:
The patent removes the unit gain buffer component entirely from the design. Instead of adding buffering stages to stabilize reference voltage, the invention achieves stability through direct low-impedance connections and proper circuit layout with separate ground paths, eliminating the area overhead of additional buffer circuits.
Solution Approach 2:
The patent uses separate metal traces as intermediaries to connect the reference voltage generation circuit to the MDAC. These dedicated traces provide low-impedance paths that stabilize the reference voltage delivery without requiring active buffering components, thus avoiding area increase while maintaining operation stability.
Data Source
AI summary
The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.