Pipelined ADC Stage Layout for Faster Time-Parallel Conversion
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Solution Overview
Problem
Current pipelined analog-to-digital converters (ADCs) are not optimized in terms of time sequence, leading to suboptimal conversion rates and increased chip area due to high technical circuit complexity.
Innovation Solution
The method involves using a dual sample-and-hold circuit architecture where the analog input signal is stored during one cycle and amplified and converted in parallel during the next cycle, allowing for simultaneous operation of the AD/DA conversion path with the amplifier and memory device, reducing overall conversion time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional pipelined ADC architecture is used, then high conversion rate is achieved, but chip area increases due to high circuit complexity
Solution Approach 1:
The converter stage is divided into two parallel paths: an amplifier path and an AD/DA conversion path. This segmentation allows independent optimization of each path and enables time-parallel operation, reducing the required chip area while maintaining high conversion rates.
Solution Approach 2:
The invention uses periodic sampling with sample-and-hold circuits that operate in alternating cycles (odd cycles for storing input signals, even cycles for processing). This periodic action enables time-parallel operation of the amplifier and AD/DA conversion paths, effectively doubling the conversion rate while using the same hardware resources.
2Productivity
If the ADC architecture is optimized for high conversion rate, then productivity increases, but device complexity increases
Solution Approach 1:
The sample-and-hold circuits serve multiple functions: they act as input buffers, timing controllers, and signal storage elements. The same hardware infrastructure is used for both amplification and AD/DA conversion by alternating their operation in different cycles, reducing overall device complexity.
Solution Approach 2:
The invention transitions from spatial parallelism (multiple converters operating simultaneously) to temporal parallelism (single converter operating in time-multiplexed fashion). By adding the time dimension to the conversion process, the system achieves higher conversion rates without proportionally increasing circuit complexity.
3Loss of time
If time-parallel operation is implemented, then conversion time is reduced, but device complexity increases
Solution Approach 1:
The system uses periodic sampling cycles where odd cycles are dedicated to storing input signals and even cycles to processing. This periodic alternation enables time-parallel operation of the amplifier and AD/DA conversion paths, effectively halving the conversion time while using a single converter stage.
Solution Approach 2:
Input signals are pre-stored in sample-and-hold circuits during odd cycles before processing begins in even cycles. This preliminary action prepares the signals in advance, enabling seamless time-parallel operation and reducing overall conversion time without requiring additional processing hardware.
Data Source
AI summary
A pipelined analog-to-digital converter has an analog signal input. A first input sample-and-hold circuit is connected to the analog signal input. An amplifier is connected to an output of the first input sample-and-hold circuit. A second input sample-and-hold circuit has an input connected to the analog signal input in parallel to the first input sample-and-hold circuit. An AD/DA conversion path is connected to an output of the second input sample-and-hold circuit. A first output sample-and-hold circuit has an input connected to an output of the amplifier. A second output sample-and-hold circuit has an input connected to the output of the amplifier. The amplifier, the first output sample-and-hold circuit, the second input sample-and-hold circuit, and the AD/DA conversion path are part of a converter stage and outputs of the converter stage are inputs to a following converter stage.