Cyclic ADC Timing Control for High-Resolution Fast Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
General cyclic analog-to-digital converters face a trade-off between resolution and conversion time, where improving resolution leads to increased error amplification and power consumption due to fixed cycle processing periods.
Innovation Solution
An analog-to-digital converter with a cycle processing unit that shortens cycle processing periods based on the cycle number, using a comparator, D/A converting circuit, amplifier, and sample holding circuit to accurately convert analog signals into digital signals with controlled sampling times, thereby reducing error amplification and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the settling time is increased to reduce error in each cycle, then the resolution of the A/D converter is improved, but the period of cycle processing increases and the total A/D conversion time increases
Solution Approach 1:
The patent applies dynamics by making the cycle processing period variable rather than fixed. The control unit dynamically adjusts the period length based on the cycle number: longer periods are used in early cycles when error amplification is more critical, and shorter periods are used in later cycles. This dynamic adjustment allows the system to maintain high resolution while reducing total conversion time compared to uniform period approaches.
Solution Approach 2:
The patent changes the parameter of cycle processing period based on the cycle number. Specifically, the period is set to be longer in earlier cycles (where error amplification has greater impact on final resolution) and shorter in later cycles. This parameter change strategy optimizes the trade-off between error reduction and conversion speed, resolving the contradiction between resolution and conversion time.
2Measurement precision
If the number of cycle processing is increased to improve resolution, then the resolution can be improved, but the power consumption increases
Solution Approach 1:
The patent uses dynamic adjustment of cycle processing period to reduce the number of cycles needed for achieving target resolution. By optimizing the period length according to cycle number, the system achieves high resolution more efficiently, reducing unnecessary cycles and thereby lowering power consumption while maintaining measurement precision.
Solution Approach 2:
The control unit automatically adjusts the cycle processing period based on the cycle number without external intervention. This self-service mechanism optimizes the conversion process in real-time, ensuring that each cycle contributes maximally to resolution while minimizing energy waste from excessive or poorly-timed cycles.
3Device complexity
If the cycle processing period is fixed, then the control is simple, but the error amplification from high-order bits limits the resolution
Solution Approach 1:
The patent implements dynamic control where the cycle processing period varies according to the cycle number. The control unit uses a simple rule (period depends on cycle number) to achieve complex optimization: longer periods in early cycles reduce error amplification impact, while maintaining relatively simple control logic. This resolves the contradiction between control simplicity and resolution achievement.
Solution Approach 2:
The patent changes the control parameter (cycle processing period) based on cycle number to optimize resolution. By systematically varying the period parameter, the system compensates for error amplification effects without requiring complex control algorithms, thus maintaining manageable device complexity while significantly improving measurement precision.
Data Source
AI summary
An analog-to-digital converter includes a cycle processing unit and a control unit. The cycle processing unit converts an analog input signal into a digital signal having a plurality of bits by performing a plurality of cycle processing on the analog input signal to acquire values of each bit in order from a higher-order bit to a lower-order bit. The control unit controls the cycle processing unit such that a period of the cycle processing is shortened according to a cycled number of the cycle processing.