Columnar Programmable Fabric With NoC Memory Controller Routing
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Solution Overview
Problem
Programmable logic devices face challenges in efficiently routing signals and managing data throughput due to limitations in their interconnect systems, leading to performance bottlenecks and reduced configuration flexibility.
Innovation Solution
The integration of a network-on-chip (NoC) interconnect system and programmable interconnect fabric, which selectively routes data between I/O interface circuits and programmable logic, using packetized data protocols to alleviate signal routing burdens and increase data processing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional programmable interconnect fabric is used to route signals between I/O blocks and programmable logic, then the device structure remains simple and manageable, but signal routing latencies increase and data processing speeds decrease due to routing bottlenecks
Solution Approach 1:
The interconnect system is segmented into two distinct parts: a traditional programmable interconnect fabric for general-purpose routing and a novel network-on-chip (NoC) interconnect system for high-speed data transport. This segmentation allows each subsystem to be optimized for its specific function, with the NoC handling bandwidth-intensive operations and the programmable fabric handling flexible routing, thereby increasing data processing speed without overwhelming the control logic.
Solution Approach 2:
The NoC interconnect system acts as an intermediary between the I/O blocks and the programmable logic, providing a dedicated high-speed data path that bypasses the limitations of the traditional programmable interconnect fabric. This intermediary structure reduces signal routing latencies by handling data transport independently, allowing the programmable fabric to focus on logic operations rather than data movement bottlenecks.
2Adaptability or versatility
If more I/O interface circuits are integrated into the device, then configuration flexibility and functionality increase, but the existing interconnect system becomes overwhelmed and performance bottlenecks occur
Solution Approach 1:
The patent introduces a new dimension to the interconnect architecture by adding the NoC system with its own dedicated routing resources and data paths. This dimensional expansion allows multiple I/O interface circuits to access programmable logic simultaneously through parallel NoC channels, preventing the single-bus bottleneck of traditional architectures and enabling data throughput to scale with the number of I/O interfaces.
Solution Approach 2:
The NoC interconnect system provides universal high-speed access to programmable logic from any I/O interface circuit in the device. This multi-functional capability allows the same NoC infrastructure to serve multiple I/O blocks concurrently, enabling configuration flexibility to increase without proportionally increasing routing complexity or creating performance bottlenecks.
3Ease of operation
If the programmable interconnect fabric is used for all data routing operations, then the system remains uniform and easy to control, but signal routing latencies increase and overall device performance decreases
Solution Approach 1:
The system dynamically selects between two routing paths based on operational requirements: the programmable interconnect fabric for flexible, control-intensive operations and the NoC interconnect system for time-critical data transport. This dynamic allocation allows the system to maintain ease of operation through unified configuration interfaces while reducing signal routing latencies by automatically utilizing the faster NoC path when available.
Data Source
AI summary
Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.