Multi-Stage SAR ADC Reference Generation for Fast Low-Power Conversion
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Solution Overview
Problem
Existing analogue to digital converters (ADCs), particularly successive approximation register (SAR) ADCs, face challenges in achieving high speed and low power consumption, especially when processing multiple signals in parallel, due to the need for precise and power-hungry circuitry for generating reference signals.
Innovation Solution
The proposed solution involves a multi-channel SAR ADC design with a controller that signals multiple voltage generators to estimate bits of the digital representation in two stages, allowing for relaxed performance requirements in the second stage, reducing power consumption and circuit area by using fewer and less precise voltage generators for less significant bits, and employing a single voltage generator for finer resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple voltage generators are used to determine multiple bits in parallel, then conversion speed is improved, but power consumption and circuit area increase
Solution Approach 1:
The conversion process is segmented into two stages: a first stage that determines more significant bits using multiple voltage generators in parallel, and a second stage that determines less significant bits using fewer voltage generators. This segmentation allows the system to achieve high conversion speed for the most critical bits while reducing power consumption for the less critical bits.
Solution Approach 2:
Different numbers of voltage generators are allocated to different bit significance levels. The first stage uses V1 voltage generators to determine B1 more significant bits, while the second stage uses V2 fewer voltage generators to determine B2 less significant bits. This local quality differentiation optimizes the balance between speed and power consumption based on the varying importance of different bit positions.
2Speed
If multiple voltage generators are used to determine multiple bits in parallel, then conversion speed is improved, but circuit area increases
Solution Approach 1:
The circuit is segmented into two operational stages with different resource allocations. The first stage employs multiple voltage generators to achieve parallel bit determination and high speed, while the second stage uses fewer voltage generators, thereby reducing the overall circuit area requirement while maintaining acceptable conversion speed.
Solution Approach 2:
The circuit allocates voltage generators non-uniformly across different conversion stages. The first stage uses V1 voltage generators for B1 bits, and the second stage uses V2 voltage generators for B2 bits, where V2 < V1. This local quality approach reduces total circuit area by using fewer generators for less significant bits where full parallelism is not critical.
3Use of energy by moving object
If fewer voltage generators are used, then power consumption is reduced, but measurement precision deteriorates
Solution Approach 1:
The system applies different numbers of voltage generators to different bit significance levels. More significant bits (first stage) use V1 voltage generators for high precision, while less significant bits (second stage) use V2 fewer voltage generators. This local quality differentiation maintains overall measurement precision by ensuring that the most critical bits are determined with high accuracy while accepting reduced precision for less critical bits.
Solution Approach 2:
The bit determination process is segmented into two precision levels. The first stage determines B1 more significant bits with higher precision using V1 voltage generators, while the second stage determines B2 less significant bits with reduced precision using V2 voltage generators. This segmentation allows the system to maintain adequate overall precision while reducing power consumption.
Data Source
AI summary
An analog to digital converter comprising: a plurality of voltage generators, each voltage generator having a control input and being capable of generating an output whose voltage is dependent on a signal applied to the control input; a comparison stage arranged to compare the input signal with one or more outputs of the voltage generators and generate one or more comparator outputs indicative of the result(s) of the comparison(s); and a controller arranged to receive the comparator outputs, the controller being configured to: (i) signal the control inputs of a number V1 of the voltage generators, and estimate a number B1 of bits of the digital representation; and subsequently (ii) signal the control input(s) of a number V2 of the voltage generators, and estimate a number B2 of bits of the digital representation; wherein V2 is less than V1.