Interleaved ADC Equalization Using Fast FIR Filtering
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Solution Overview
Problem
High-speed analog to digital converters (ADCs) with time interleaved sub-ADCs face challenges in reducing spurious frequency components due to misaligned amplitude and phase frequency responses, leading to signal distortions, and existing equalization methods require a large number of multipliers, making real-time operation difficult.
Innovation Solution
Applying Fast Filtering Algorithms to an equalizer built as a set of switched FIR filters with constant coefficients, reducing the number of multipliers needed and simplifying the design by using Pre-FIR and Post-FIR transformers to replace conventional FIR filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FIR filters are used in the equalizer, then the equalization performance is adequate, but the number of multipliers required is large, making real-time operation difficult
Solution Approach 1:
The patent transforms the conventional FIR filter structure by changing the computational parameters - specifically by applying fast filtering algorithms that reduce the number of multiplications required. This is achieved by reorganizing the filter coefficients and computation sequence to exploit symmetries and redundancies in the filtering operation, thereby reducing computational complexity while maintaining equalization performance.
Solution Approach 2:
The patent replaces the conventional mechanical multiplication operations with an equivalent computational system that uses fewer multipliers. By substituting the standard FIR filter computation mechanism with a fast filtering algorithm that uses addition and shifting operations more efficiently, the system achieves the same filtering effect with reduced hardware complexity and improved real-time processing capability.
2Productivity
If the number of sub-ADCs is increased to achieve higher sampling rates, then the conversion rate increases, but the misalignment of frequency responses causes more severe signal distortions
Solution Approach 1:
The patent implements a feedback mechanism through the equalizer that continuously compensates for the frequency response misalignment caused by multiple sub-ADCs. The equalizer receives the combined output from all sub-ADCs and applies corrective filtering that counteracts the distortion effects, thereby maintaining signal quality even as the number of sub-ADCs increases to achieve higher sampling rates.
Solution Approach 2:
The patent introduces an equalizer as an intermediary component between the multiple sub-ADCs and the final output. This intermediary device processes the combined signals from all sub-ADCs and corrects the frequency response misalignment before the final output is produced, thereby eliminating the harmful distortion effects while preserving the high sampling rate capability.
3Measurement precision
If time varying FIR filters are used for equalization, then the equalization accuracy is improved, but the device complexity and number of multipliers increase significantly
Solution Approach 1:
The patent segments the time-varying equalization function into multiple constant-coefficient FIR filters that are switched in sequence. Instead of using a single complex time-varying filter with many multipliers, the system divides the equalization task into several simpler filter stages, each with constant coefficients, that are activated at different times to collectively achieve the desired time-varying equalization effect with reduced computational complexity.
Solution Approach 2:
The patent employs periodic switching between multiple constant-coefficient FIR filters to achieve time-varying equalization. By periodically switching between these simpler filters in a predetermined sequence, the system approximates the effect of a continuous time-varying filter while using significantly fewer multipliers and reducing device complexity, thus maintaining equalization accuracy with reduced hardware requirements.
Data Source
AI summary
A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.