ADC Test Circuit Switching for Single-Insertion SNR and INL
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current ADC testing systems require two separate insertions to evaluate noise performance and integral non-linearity, increasing testing time due to the trade-off between fast settling time and low noise, as they use separate circuits for each evaluation.
Innovation Solution
A method and system that utilize three test modes to compute the ADC's signal-to-noise ratio (SNR) by connecting ADC input terminals, applying zero and full-scale source voltage signals, and calculating noise values using standard deviations and Fast Fourier Transform, allowing for a single insertion to assess both noise performance and integral non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two separate circuits are used for testing ADC noise and integral non-linearity, then measurement precision for both parameters is improved, but testing time increases due to requiring two separate insertions
Solution Approach 1:
The patent combines two separate test circuits (low noise test circuit and fast settling-time test circuit) into a single integrated test circuit that can perform both noise performance testing and integral non-linearity testing. This merging eliminates the need for two separate ADC insertions, thereby reducing testing time while maintaining measurement precision for both SNR and INL parameters through selective activation of different circuit paths.
Solution Approach 2:
The test circuit is designed with multi-functionality to handle both noise measurement and INL measurement within a single insertion. The circuit includes a low noise path for SNR measurement and a fast settling path for INL measurement, allowing the same physical test setup to serve multiple testing purposes without requiring separate dedicated circuits for each function.
2Measurement precision
If a low noise test circuit is used to evaluate SNR performance, then measurement precision for noise is improved, but settling time increases
Solution Approach 1:
The test circuit employs dynamic switching between different operational paths based on the measurement being performed. A switch selectively connects the ADC input to either the low noise path (for SNR measurements requiring high precision but accepting longer settling time) or to a fast settling path (for INL measurements requiring quick response). This dynamic reconfiguration allows the circuit to optimize performance characteristics according to the specific measurement task.
Data Source
AI summary
Disclosed examples include a method and automated test system for testing an ADC. The method includes computing an ADC noise value based on a first set of data values sampled while the ADC input terminals are shorted, computing a first system noise value based on a second set of data values sampled while a test circuit signal source applies zero volts to the ADC through a signal chain, computing a signal chain noise value based on the first system noise value and the ADC noise value, computing a measured SNR value based on a third set of data values sampled while the test circuit signal source applies a non-zero source voltage signal to the signal chain, computing a second system noise value based on the measured SNR value, and computing an ADC SNR value based on the second system noise value and the signal chain noise value.