Time-Interleaved ADC Clock Skew Correction by Max-Value Averaging
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Solution Overview
Problem
Current analog to digital converter (ADC) technologies face challenges in reducing clock skew errors, which require complex circuits or off-chip calibration, leading to higher power consumption and longer correction cycles.
Innovation Solution
The proposed solution involves a time-interleaved ADC device with a calibration circuitry and skew adjustment circuitry that performs calibration operations on quantization outputs to generate adjustment signals, reducing clock skew without additional ADC circuits by averaging maximum value signals and comparing them with a reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex circuits (additional reference ADC or auxiliary ADC) are used to calibrate timing error, then timing error calibration is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts the timing error calibration function from complex ADC circuits and implements it using a simplified digital processing approach. By taking out the calibration function and implementing it separately through max value detection and phase comparison, the device eliminates the need for additional reference ADC or auxiliary ADC circuits, thereby reducing device complexity while maintaining calibration precision.
Solution Approach 2:
The patent creates a digital copy of the calibration process using max value signals that represent the quantization outputs. Instead of using physical additional ADC circuits, the invention copies the calibration function into the digital domain where it can be implemented through simple logic operations (max value detection, averaging, and phase comparison), significantly reducing hardware complexity.
2Measurement precision
If complex circuits (additional reference ADC or auxiliary ADC) are used to calibrate timing error, then timing error calibration is improved, but power consumption increases
Solution Approach 1:
The patent extracts the timing error calibration function from power-hungry ADC circuits and implements it using low-power digital processing. By separating the calibration function from the main ADC operation and implementing it through simple digital operations (max value detection, averaging, and phase comparison), the invention dramatically reduces power consumption while maintaining calibration accuracy.
Solution Approach 2:
The patent replaces expensive, power-consuming ADC circuits with inexpensive digital processing operations. The calibration is achieved through simple digital steps (detecting max values, averaging them, and comparing phases) that consume minimal power compared to running additional ADC circuits, effectively using low-cost computational methods to achieve high-precision calibration.
3Measurement precision
If off-chip calibration is performed to calibrate timing error, then timing error calibration is improved, but calibration cycle time increases
Solution Approach 1:
The patent merges the timing error calibration function with the main ADC operation by implementing it on-chip within the same device. The calibration process is integrated into the normal operation flow, allowing calibration to be performed simultaneously with or immediately following normal conversion operations, thereby eliminating separate calibration cycles and reducing total calibration time.
Solution Approach 2:
The patent performs preliminary calibration actions by detecting max values and computing average phase references during normal operation. The calibration data is prepared in advance and used immediately for timing error correction, eliminating the need for separate, time-consuming calibration cycles that would otherwise be required to achieve the same precision.
Data Source
AI summary
An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjustment circuitry. The ADC circuitries are configured to convert an input signal according to interleaved clock signals, in order to generate first quantization outputs. The calibration circuitry is configured to perform at least one calibration operation according to the first quantization outputs, in order to generate second quantization outputs. The skew adjustment circuitry is configured to determine maximum value signals, to which the second quantization outputs respectively correspond during a predetermined interval, and to average the maximum value signals to generate a reference signal, and to compare the reference signal with each of the maximum value signals to generate adjustment signals, in order to reduce a clock skew of the ADC circuitries.