Folded Current Sampler Circuit for Gain and S11 Trade-Offs

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Solution Overview

Problem

Current sampler circuitry faces challenges in achieving high bandwidth and gain while maintaining a good S11 performance, with a strong trade-off between gain and S11 parameter, and suffers from low voltage headroom and difficulty in current scaling, especially in high-resolution applications.

Innovation Solution

The implementation of a 'folded' sampler circuitry using current mirror circuitry, which separates the primary and secondary current paths, allowing for programmable gain and improved S11 performance by decoupling S11 from the load circuitry, and includes impedance configurations such as resistors, inductors, and capacitors to enhance gain at high frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional sampler circuitry is used to achieve high gain, then the S11 performance deteriorates

Engineering Contradiction:
ImprovegainVSAvoidS11 performance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The circuit is divided into separate primary and secondary current paths. The primary path handles voltage-to-current conversion with optimized S11 performance, while the secondary path provides gain through current mirroring. This segmentation allows independent optimization of each path for its specific function, resolving the trade-off between gain and S11 performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A current mirror circuit acts as an intermediary between the primary current path and the load circuitry. It transfers and amplifies the current signal while isolating the S11-critical input stage from the gain-providing output stage, enabling both high gain and good S11 performance simultaneously.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If voltage headroom is increased to improve current scaling, then the circuit complexity increases

Engineering Contradiction:
Improvecurrent scalingVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The circuit employs dynamic current mirroring techniques where the current scale factor can be programmably adjusted through control signals that modify the mirroring ratio. This dynamic adaptability allows current scaling without requiring multiple fixed circuits, reducing overall complexity while maintaining versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit uses programmable parameters (such as control voltages or currents) to adjust the current scaling factor. By changing electrical parameters rather than physical circuit topology, the circuit achieves adaptable current scaling with minimal complexity increase.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances bandwidth, reduces voltage headroom, and improves current scaling, achieving higher gain and better S11 performance, enabling more efficient and compact high-resolution applications.

Implementation Method 1

The current mirror circuitry comprises a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path

Methodology Applied
Scientific EffectCurrent mirror effect:

Data Source

PatentUS10951223B2Current signal generation useful for sampling
Publication Date: 2021.03.16 SOCIONEXT INC
  • US10951223B2 patent drawing
  • US10951223B2 patent drawing
  • US10951223B2 patent drawing

AI summary

Sampler circuitry including load circuitry having sampler switches to sample first and second load currents, the load circuitry having first and second load nodes and a biasing node; a power supply node connected to a voltage source; a first current path extending from the power supply node to the first load node to provide the first load current at the first load node, where a first supply-connection impedance is connected along the first current path; a second current path extending, in parallel with the first current path, from the power supply node to the second load node to provide the second load current at the second load node for use by the load circuitry, where a second supply-connection impedance is connected along the second current path between the power supply node and the second load node; first and second input-connection impedances; and control circuitry.