Synchronized Charge Pump Input Buffer for Low-Noise Negative Signal ADC
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Solution Overview
Problem
Existing integrated circuits require an external negative power supply to digitize signals at ground or below ground, increasing system cost and complexity, particularly for on-chip analog-to-digital converters.
Innovation Solution
An integrated circuit design that uses an oscillator circuit to generate clock signals for both the ADC and charge pump, with specific frequency ratios to minimize timing errors and clock feed-through noise, allowing digitization of negative signals without an external negative power supply by selecting a charge pump frequency that falls within the rejection band of the ADC's digital filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an external negative power supply is used to drive the negative rail of the input buffer, then the ADC can digitize signals at ground or below ground, but the system cost and complexity increase
Solution Approach 1:
The patent combines the negative power supply function with the existing positive power supply and ADC circuitry by using a charge pump circuit that generates the negative voltage internally. This merging eliminates the need for a separate external negative power supply while maintaining the ability to digitize signals at ground or below ground.
Solution Approach 2:
The ADC system becomes self-sufficient by generating its own negative power supply voltage through the integrated charge pump circuit. The circuit uses the existing positive supply voltage and clock signals to create the required negative bias voltage, eliminating dependence on external negative power sources.
2Adaptability or versatility
If an external negative power supply is used, then the ADC can process negative signals, but the total system cost increases
Solution Approach 1:
The patent merges the negative power supply functionality into the existing ADC system, using the same chip and manufacturing process. This integration eliminates the need for additional external components and reduces overall system cost while maintaining the ability to process negative signals.
Solution Approach 2:
The charge pump circuit serves multiple functions: it generates the negative bias voltage for the input buffer, uses existing clock signals from the system, and operates within the existing power supply framework. This multi-functionality reduces the need for dedicated components and lowers system cost.
3Device complexity
If a charge pump is used to generate negative voltage, then an external negative power supply is eliminated, but clock feed-through noise is introduced
Solution Approach 1:
The patent converts the potentially harmful clock feed-through noise into a beneficial arrangement by carefully selecting the charge pump clock frequency to fall within the rejection band of the ADC's digital filter. The noise is not eliminated but is positioned where it can be effectively rejected by the existing filtering architecture.
Solution Approach 2:
The patent changes the frequency parameter of the charge pump clock to achieve a specific relationship with the ADC sampling frequency. By setting the charge pump clock frequency to a sub-multiple of the ADC sampling frequency, the noise falls into the digital filter's rejection band, transforming a harmful effect into an acceptable one.
4Object-generated harmful factors
If the charge pump frequency is increased to reduce noise, then noise interference is minimized, but timing errors between ADC and charge pump increase
Solution Approach 1:
The patent changes the frequency parameter to achieve an optimal balance: the charge pump clock frequency is set to a specific sub-multiple of the ADC sampling frequency. This parameter selection simultaneously places noise in the filter rejection band while maintaining precise timing relationships through the synchronized clock architecture.
Solution Approach 2:
The patent employs a synchronized charge pump architecture where the charge pump clock is derived from the same clock source as the ADC, creating a feedback relationship between the two circuits. This feedback mechanism ensures that timing errors are minimized while the frequency relationship maintains noise in the rejection band.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the digitization of signals at ground or below ground without an external negative power supply, reducing system complexity and cost while minimizing noise interference, thereby improving the accuracy of ADC conversions.
Implementation Method 1
a charge pump circuit to pump a charge from a ground to a negative power supply node of the input buffer
Implementation Method 2
an oscillating circuit to generate a frequency of the charge pump clock signal that is a sub-multiple of a frequency of the ADC sampling clock signal
Data Source
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AI summary
An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.