Neural Network Circuits With Early MSB Integration Before ADC
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Solution Overview
Problem
In neural network computing, the large size and area-inefficiency of Analog-to-Digital Converter (ADC) circuitry lead to significant time delays in performing ADC operations, data transmission, and preparing pulse-modulated data for subsequent arrays, necessitating a method for rapid pulse-modulated integration.
Innovation Solution
The implementation of early integration by transmitting the most significant bit (MSB) before Analog-to-Digital Conversion, allowing parallel processing and transmission of analog voltages and digital values, with a comparator generating bits indicating threshold exceedance and a modulator providing pulses proportional to digital values, enabling efficient integration at subsequent arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ADC conversion is performed before integration, then integration accuracy is improved, but processing time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing integration on the most significant bit (MSB) of the analog signal before the complete ADC conversion is finished. The MSB is extracted and integrated early at the second synaptic array while the remaining bits are still being converted, thereby reducing the total processing time without sacrificing integration accuracy.
Solution Approach 2:
The patent segments the ADC conversion process by separating the most significant bit (MSB) from the remaining bits. The MSB is processed and integrated separately and earlier than the other bits, allowing parallel processing and reducing the critical path delay of the overall system.
2Measurement precision
If ADC circuitry is made larger to improve conversion capability, then conversion precision is improved, but area efficiency deteriorates
Solution Approach 1:
By extracting and processing the MSB before the full ADC conversion completes, the patent reduces the burden on the ADC circuitry. This allows the use of a smaller, more area-efficient ADC while maintaining the ability to achieve high conversion precision through the combination of early MSB integration and subsequent processing of remaining bits.
3Productivity
If parallel processing is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent implements parallel processing by having the second synaptic array begin integration of the MSB before the ADC conversion of remaining bits is complete. This preliminary action creates natural parallelism in the processing pipeline, improving throughput while adding minimal complexity since the parallel path simply waits for the MSB to be ready.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall time required for integration by allowing early integration of the MSB, completing remaining integration tasks before the completion of ADC operations, thereby saving approximately half the maximum duration and enhancing operational efficiency.
Implementation Method 1
At least one comparator is operatively coupled to the first synaptic array. The at least one comparator is adapted to compare the plurality of analog voltages to a predetermined threshold to generate a vector of bits
Implementation Method 2
The at least one analog-to-digital converter is configured to convert the plurality of analog voltages to a vector of digital values
Implementation Method 3
The at least one modulator is configured to receive the vector of bits from the network, process the vector of bits, said processing the vector of bits comprising providing a pulse to each of the plurality of input wires of the second synaptic array when a corresponding bit of the vector of bits indicates that the predetermined threshold was exceeded
Data Source
AI summary
Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the vector of bits via a network. At least one ADC is configured to convert the plurality of analog voltages to a vector of digital values, and transmit the vector of digital values via the network. At least one modulator is configured to receive the vector of bits from the network, provide pulses to each of a plurality of input wires of a second synaptic array based on the vector of bits, receive the vector of digital values from the network, and provide pulses to each of the plurality of input wires based on the vector of digital values.