Radar Front End Serial Data Interface for Embedded Timing

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Solution Overview

Problem

Radar systems face signal degradation and increased power consumption due to the separation between analog and digital domains, requiring multiple wires for data and synchronization signals, which complicates the interface between the analog front end and digital back end.

Innovation Solution

An analog front end that includes a transmitter circuit, receiver circuit, timing circuit, converter, and serializing circuit to combine valid data signals with radar data into a single serial data stream, reducing the need for separate synchronization signals and wires.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a digitized version of the sensitive analog radar signal is sent from the analog frontend to the digital baseband, then signal degradation is reduced, but the number of physical wires required increases

Engineering Contradiction:
Improvesignal degradationVSAvoidnumber of physical wires
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple separate signal transmission functions into a single differential pair. The radar data stream, valid data timing signal, and synchronization signals (bit clock and frame clock) are all encoded and transmitted through the same physical medium, eliminating the need for multiple separate wires while maintaining signal integrity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The differential pair is designed to serve multiple functions simultaneously: it carries the digitized radar data, conveys timing information through valid data signals, and provides synchronization through embedded clock signals. This multi-functional approach reduces the overall wire count while maintaining all necessary communication capabilities

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If separate synchronization signals are supplied from the front end to the baseband processor, then timing accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent merges the timing information into the data stream itself by using valid data signals that indicate when the receiver will be receiving reflected radar signals. These timing signals are transmitted through the same differential pair as the data, eliminating the need for separate high-power synchronization signal transmission paths

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system uses the data transmission medium itself to carry the timing information needed for synchronization. The valid data signals embedded in the stream provide the baseband processor with the timing information it needs, making the data stream self-sufficient for both data and timing functions

Inventive Principle:
Principle #25Self-service

3Reliability

If multiple wires are used to carry digital data and synchronization signals, then signal integrity is maintained, but the interface complexity between analog front end and digital back end increases

Engineering Contradiction:
Improvesignal integrityVSAvoidinterface complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent consolidates multiple signal types (radar data, valid data timing, bit clock, frame clock) into a single differential pair transmission. This reduces the physical interface complexity while maintaining signal integrity through the use of differential signaling, which is inherently more noise-resistant than single-ended signaling

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10627505B2Front end for a radar system and method of operation a front end for a radar system
Publication Date: 2020.04.21 NXP BV
  • US10627505B2 patent drawing
  • US10627505B2 patent drawing
  • US10627505B2 patent drawing

AI summary

A front end for a radar system and method of operation are described. A timing circuit controls operation of a transmitter circuit and a receiver circuit and outputs a valid data signal indicating whether the receiver circuit will be receiving a reflected radar signal. A converter converts a received radar signal and outputs digital data. A serialising circuit receives the digital data and supplies a serial data stream including the digital data for a data processing device. The valid data signal is also communicated to the converter to cause the converter to output a bit pattern corresponding to a code word when the valid data signals indicates that the receiver circuit will not be receiving the reflected radar signal and to output a bit pattern corresponding to a data word including radar data when the valid data signals indicates that the receiver circuit will be receiving the reflected radar signal.