ADC Comparator Offset Calibration Using Reference Shuffling
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Solution Overview
Problem
Existing delta-sigma (ΔΣ) analog-to-digital converters (ADCs) face significant challenges due to quantization noise from flash comparators, which can be near the same level as thermal noise, leading to failure in meeting noise specifications without proper calibration, especially due to manufacturing imperfections like comparator offsets.
Innovation Solution
A calibration system that includes a noise source, an internal ADC, a reference shuffling circuit, a calibration circuit, and calibration logic to adjust comparator offsets, using schemes like data weighted average, leap-frogging, and swapping to ensure comparators experience transitions, and employing algorithms such as random walk, simulated annealing, or genetic algorithms to optimize calibration codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If quantization noise from flash comparators is reduced through calibration, then noise specifications are met, but device complexity increases due to additional calibration circuits and algorithms
Solution Approach 1:
The calibration system uses the ADC's own output to measure quantization noise and automatically adjusts comparator offsets through embedded calibration logic, eliminating the need for external calibration equipment and reducing overall system complexity
Solution Approach 2:
The calibration circuit measures the ADC output, calculates quantization noise power, and uses this feedback to iteratively adjust comparator offsets until noise specifications are met, creating a closed-loop calibration process that optimizes performance automatically
2Measurement precision
If comparator offsets are calibrated to reduce quantization noise, then measurement precision improves, but calibration time increases due to iterative optimization algorithms
Solution Approach 1:
The calibration system performs offset calibration during the manufacturing process or initial setup phase, so that by the time the ADC is deployed for actual measurements, the comparator offsets are already optimized and no additional calibration time is required during operation
Solution Approach 2:
The calibration process systematically varies comparator offset parameters using optimization algorithms (such as gradient descent or genetic algorithms) to find the optimal set of offsets that minimize quantization noise, balancing calibration time with measurement precision
3Measurement precision
If reference shuffling is implemented to ensure comparator transitions during calibration, then calibration accuracy improves, but device complexity increases due to additional shuffling circuitry
Solution Approach 1:
The reference shuffling circuit dynamically permutes the reference voltage assignments to different comparators during calibration, ensuring that each comparator experiences a full range of input conditions and transitions, which improves calibration accuracy without requiring permanent structural changes
Solution Approach 2:
The reference shuffling operates in periodic cycles during calibration, systematically rotating through different reference assignments to ensure all comparators are adequately stimulated, then settles into a stable configuration for normal operation
Data Source
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AI summary
A calibration system for an analog-to-digital converter (ADC) comprising an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.