Analogue Conversion TRIZ Cases

Adaptive toggle compensation limits switching DAC units to cut data-dependent supply noise and power draw without degrading analog output quality.

Simultaneous single-node drive and sensing with differential feedback and sigma-delta noise shaping improves touch accuracy without extra integration cycles.

Clock-gated latch timing shifts the data crossing point to avoid short-circuit current and power-line ripple in DAC circuits.

Parallel partitioning lets a delta-sigma modulator meet high-speed transmitter timing with less analog circuitry, smaller area, and lower power.

Injected dither and differential counting isolate sampler and amplifier nonlinearity in ADCs, cutting convergence time and power use.

Centered modulo sampling in a self-reset ADC avoids clipping and reconstructs bandlimited signals without fold-count hardware.

A two-phase accumulation loop combines linear weighting and exponential SQNR boosting to improve SNDR, dynamic range, and conversion speed.

Direct differential feedback removes the common-mode loop and reference current, simplifying a sigma-delta modulator while lowering noise.

Threshold-based reversal of integration direction expands capacitance sensing range while improving SNR and robustness to sensor variation.

MIMO filtering shapes quantization errors across space and time, improving coarse sensor array precision with lower quantizer complexity.

Oversampling and noise shaping let one interface digitize LTE, Wi-Fi, and 5G-NR carriers for spectral-efficient fronthaul with simpler RRHs.

Chopping resolves MSBs while CDS handles Nyquist LSB scaling, reducing offset and flicker noise without sacrificing ADC accuracy.

Oversampled delta-sigma digitization carries aggregated 4G, Wi-Fi, and 5G signals with higher fronthaul efficiency and fewer RRH components.

By switching integration direction and counting reversals, this circuit extends touch and fingerprint sensing voltage range without changing capacitor values.

Periodic reset and mode switching let the analog amplifying unit deliver high-resolution delta-sigma conversion with faster speed and lower power.

Direct RF digitization with resonant bandpass delta-sigma ADCs removes mixers and analog IQ paths to cut noise, power use, and image tones.

Reference-path dither swaps comparator references in a sigma-delta ADC to randomize mismatch errors and cut harmonic distortion without extra area or power.

By digitizing RF samples for digital optical transport, this case improves HFC link budget, nonlinear noise tolerance, and transmission distance.

A recombiner and dual-quantizer feedback loop cut quantization noise while preserving fast ADC response and wide bandwidth.

A dual-loop sigma-delta sensor uses multi-bit feedback with a single-bit quantizer to cut power and noise without phase-compensating filters.

Multiple feedback combines SAR residue generation with delta-sigma noise shaping to raise ADC resolution at high speed with lower comparator noise.

Differential noise around resonance tunes a delta-sigma loop filter in closed control loops without interrupting readout or adding extra filters.

Constant noise-shaping coefficients and tunable loop delay let one RF Sigma-Delta modulator cover multiple bands with lower tuning complexity and power.

Segmented A-bit and (N-A)-bit memory cuts hardware and memory size in a multi-channel digital sigma-delta modulator.

Segmented sigma-delta feedback keeps capacitive sensor signals within amplifier range, avoiding clipping and distortion without losing information.

A mode-selectable sigma-delta microphone circuit switches resolution, clocking, and cascaded stages to balance dynamic range and power use.

An on-chip AC filter uses a coupling capacitor and opposite diodes to block microphone DC while preserving dynamic range and audible signals.

Bit-reducing noise shaping lets a CT sigma-delta modulator use DAC MSBs only, cutting DAC area and critical path delay.

Digital droop compensation and noise-transfer zero matching cut charge pump distortion while preserving dynamic range and power efficiency.

Bitstream-driven range control adjusts the feedback subtrahend to avoid integrator saturation and preserve wide dynamic range.

A delta-sigma resolver signal chain preserves fine time resolution for tighter loop synchronization and more accurate digital measurement.

Low-side sense resistors and a sigma-delta ADC enable accurate bidirectional speaker current measurement with less circuit area and complexity.

Non-switched capacitors introduce transfer-function zeros that stabilize high-order delta-sigma ADC loops without extra analog summing circuits.

Compressing multi-bit delta-sigma ADC output cuts serial bus bit transitions and power use while preserving digital audio signal quality.

Multiple current-domain feedback loops remove pre-amplifier delay in continuous-time sigma-delta ADCs, improving stability and resolution with lower power.

A capacitor-based quantizer replaces amplifier stages to cut area, complexity, and static current in delta-sigma conversion.

Shared current-steering DACs between adjacent integrator stages cut ISI, power, and area in higher order CT sigma-delta ADCs.

A switched capacitor in the ΔΣ ADC feedback path mitigates VCO nonlinearity while preserving resolution, speed, and low circuit area.

Reference shuffling and closed-loop calibration cut ΔΣ ADC comparator offset noise, improving in-band noise and linearity.

By separating the carrier from the DPWM signal, this amplifier cuts DAC noise, improving output noise and stability.

A memoryless ADC with per-channel digital filtering avoids slow memory flushing, enabling fast cycle-by-cycle multiplexed sampling.

Extra delta-sigma samples let the AFE correct quantization noise, keeping capacitive sensing resolution high with shorter, lower-power bursts.

Phase-adjusted multi-section delta-sigma modulation disperses idle tones and cuts quantization noise in frequency ratio measurement.

Multiple sigma-delta modulations and residual error conversion raise ADC resolution without doubling clock cycles or adding complex filters.

Frequency-domain notches in the noise transfer function free passbands for extra signals while preserving low-pass signal quality in wired links.

A feed-forward path filter shifts STF peaking away from the signal band, easing pre-filter demands and supporting higher resolution.

Alternating even and odd phase connections averages digital codes to cut transistor mismatch offsets without slowing analog circuits.

Parallel oversampling branches with diplexer feedback and filter banks cut quantization noise while preserving wide bandwidth and resolution.

An error-feedback loop with a digital-to-time converter pushes quantization noise higher, improving TDC resolution with lower power.

Iterative subrange estimation lets a sigma-delta ADC adapt feedback DAC settings to keep high resolution across wide input ranges.