Sigma-Delta ADC Resolution Boosting via Residual Error Conversion
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Solution Overview
Problem
Conventional 1st order sigma delta (SD) analog-to-digital converters face a significant challenge where the number of clock cycles required for conversion doubles with each additional bit of resolution, leading to increased complexity and converter area due to higher-order decimation filters and integrators.
Innovation Solution
The proposed solution involves using multiple SD modulations on an analog value, followed by digital post-processing of pulse density modulation (PDM) streams to generate higher resolution digital outputs, with a two-phase approach: an SD phase for most significant bits (MSBs) and a resolution-boosting phase for least significant bits (LSBs, using different reference voltages and capacitor values, and combining these streams via ripple up-counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional 1st order sigma delta ADC uses higher-order decimation filters and integrators to achieve higher resolution, then measurement precision is improved, but device complexity increases and converter area increases
Solution Approach 1:
The patent segments the conversion process into multiple first-order SD conversion stages, where each stage processes a portion of the resolution. Instead of using a single high-order filter, the system divides the filtering and conversion tasks across multiple simpler first-order stages, reducing the complexity of individual components while achieving the same overall resolution.
Solution Approach 2:
The patent transitions from the time domain to the frequency domain by using digital post-processing of PDM streams. Instead of achieving resolution through time-domain integration with high-order filters, the system uses frequency-domain processing and digital filtering techniques, fundamentally changing the dimension in which resolution is achieved.
2Measurement precision
If conventional 1st order sigma delta ADC uses higher-order integrators to achieve higher resolution, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent segments the integrator function across multiple first-order stages rather than using a single high-order integrator. Each stage uses a simple first-order integrator with minimal circuit area, and the cumulative effect of multiple stages achieves the equivalent resolution of a high-order integrator without the corresponding area penalty.
Solution Approach 2:
The patent uses multiple copies of simple first-order SD converter circuits instead of a single complex high-order converter. Each copy performs a basic conversion function, and the results are combined through digital processing. This copying approach reduces the area of individual components while maintaining overall conversion accuracy.
3Measurement precision
If multiple SD modulations are applied to achieve higher resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes a single first-order SD converter circuit multi-functional by reusing it multiple times with different configurations. The same basic circuit structure serves as multiple SD modulators, each contributing to different portions of the final resolution. This universality reduces circuit complexity compared to implementing multiple dedicated high-order converter circuits.
Solution Approach 2:
The patent merges multiple PDM streams from different first-order SD conversions into a single high-resolution digital output through digital post-processing. Instead of requiring separate complex analog processing paths, the system combines multiple simple PDM streams digitally, reducing overall circuit complexity while achieving higher resolution.
Data Source
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AI summary
A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to "residual quantization error," which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.