Linear-Exponential Incremental ADC for Faster Low-Noise Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving high signal-to-noise distortion ratio (SNDR) and dynamic range (DR) due to thermal noise, non-uniform sample weightings, and power-hungry op-amps, particularly in high-order incremental ADCs, which result in long conversion times and increased power consumption.
Innovation Solution
A two-phase linear-exponential incremental analog-to-digital converter (IADC) is introduced, featuring a first-order structure for linear signal accumulation and a noise-coupling path for exponential SQNR boosting, utilizing a 17-level quantizer and ping-pong capacitor arrays to reduce thermal noise and op-amp power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-order incremental ADC structure is used to reduce the number of clock cycles, then the bandwidth increases and op-amp power consumption decreases, but the sample weightings become non-uniform, reducing the effectiveness of data weighted averaging and thermal noise suppression
Solution Approach 1:
The conversion process is segmented into two distinct phases: a linear accumulation phase that ensures uniform sample weightings for effective thermal noise suppression and DWA, and an exponential accumulation phase that accelerates convergence. This segmentation allows each phase to optimize for its specific function, resolving the contradiction between conversion speed and noise suppression effectiveness.
Solution Approach 2:
The ADC dynamically switches between linear and exponential accumulation modes based on the conversion progress. The linear phase operates initially to establish uniform weighting conditions, then transitions to exponential phase for accelerated convergence. This dynamic operation allows the system to adapt its accumulation strategy to achieve both noise suppression and fast conversion.
2Measurement precision
If a first-order incremental ADC structure is used to maintain uniform sample weightings, then thermal noise suppression and data weighted averaging are effective, but the required number of clock cycles increases to 2N for N-bit resolution, making the conversion slow
Solution Approach 1:
The conversion process is segmented into two distinct phases: a linear accumulation phase that ensures uniform sample weightings for effective thermal noise suppression and DWA, and an exponential accumulation phase that accelerates convergence. This segmentation allows each phase to optimize for its specific function, resolving the contradiction between conversion speed and noise suppression effectiveness.
Solution Approach 2:
The ADC employs periodic switching between linear and exponential accumulation phases. The linear phase operates for a predetermined number of cycles to establish uniform weighting conditions, then transitions to exponential phase for accelerated convergence. This periodic action allows the system to maintain noise suppression benefits while achieving faster overall conversion.
3Measurement precision
If second-order incremental zoom-ADC with DWA technique is used to diminish DAC mismatch errors, then linearity improves, but the linearly decreasing weighting reduces DWA effectiveness and the architecture suffers from input-clipping problem
Solution Approach 1:
The conversion process is segmented into two distinct phases: a linear accumulation phase that ensures uniform sample weightings for effective thermal noise suppression and DWA, and an exponential accumulation phase that accelerates convergence. This segmentation allows each phase to optimize for its specific function, resolving the contradiction between conversion speed and noise suppression effectiveness.
Solution Approach 2:
The accumulation weighting function is changed from linearly decreasing (second-order) to a two-phase function that maintains uniform weightings during the linear phase and then transitions to exponential accumulation. This parameter change in the weighting function preserves DWA effectiveness while achieving faster conversion and avoiding input-clipping issues.
4Measurement precision
If smart dynamic element matching algorithm is used to compensate for DAC element mismatch, then linearity improves, but the algorithm complexity increases exponentially with the order, quantizer bit, and OSR
Solution Approach 1:
The complex smart DEM algorithm is extracted and replaced with a simpler two-phase accumulation approach combined with DWA. By taking out the exponentially complex algorithm and substituting it with a more manageable two-phase method, the system achieves comparable or superior linearity with significantly reduced computational complexity that does not increase exponentially with order, quantizer bits, or OSR.
5Use of energy by moving object
If integrator slicing technique is used to reduce the first integrator's power, then power consumption decreases, but there is a tradeoff between the first integrator power and the input signal power
Solution Approach 1:
The integrator operates dynamically in two phases: during the linear phase, it processes signals with full dynamic range requirements, and during the exponential phase, the signal dynamics change allowing for reduced power operation. This dynamic operation allows the integrator to adapt its power consumption to the signal characteristics in each phase, reducing overall power requirements while maintaining signal integrity.
Data Source
AI summary
An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.