Low-Ripple Latch Circuit for Short-Circuit Current Suppression
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Solution Overview
Problem
Conventional digital-to-analog converter (DAC) latch circuits generate short-circuit currents that induce data-dependent ripples in the power line, affecting signal-to-noise ratio and total harmonic distortion in sensitive circuits.
Innovation Solution
A latch circuit design comprising an input stage, amplifying stage, and crossing point control circuit that controls the crossing point of data and inverted data values to avoid middle voltage, using cascode-connected NMOS and PMOS transistors to manage clock and data signals, and includes a clock gating circuit to prevent short-circuit currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional latch circuit outputs data values, then the data value changes from 0 to 1, but a short-circuit current is transiently generated between supply voltage and ground voltage
Solution Approach 1:
The clock gating circuit activates the clock signal before the data value transition is complete, ensuring that the crossing point of data and inverted data values occurs at an optimized voltage level rather than the middle voltage. This preliminary timing adjustment prevents the simultaneous conduction of P-type and N-type switches, eliminating the short-circuit current path while maintaining fast data output transition
2Productivity
If the latch circuit allows fast data transitions, then productivity is improved, but data-dependent ripple is induced on the power line
Solution Approach 1:
The clock gating circuit acts as an intermediary control mechanism that mediates between the data value transition and the power supply. By controlling the timing and voltage level at which the data and inverted data values cross, it prevents direct coupling of switching transients to the power line, thereby eliminating data-dependent ripple while preserving fast data transitions
3Device complexity
If the crossing point of data value and inverted data value is at middle voltage, then the latch circuit operates simply, but P-type and N-type switches switch simultaneously causing short-circuit current
Solution Approach 1:
The clock gating circuit dynamically changes the voltage parameter at the crossing point of data and inverted data values from the fixed middle voltage to a variable voltage level determined by the clock signal timing. This parameter change ensures that the crossing occurs at an optimized voltage that prevents simultaneous conduction of complementary switches, eliminating short-circuit current while maintaining circuit simplicity
Data Source
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AI summary
A latch circuit (300) includes an input stage (310), an amplifying stage (MN1, MN2, MP1, MP2) and a clock gating circuit (320). The input stage (310) is arranged for receiving at least a clock signal and a data control signal. The amplifying stage (MN1, MN2, MP1, MP2) is coupled to the input stage (310) and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit (320) is coupled to the amplifying stage (MN1, MN2, MP1, MP2), and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.