CT Sigma-Delta Modulator With Shared DAC for Lower ISI and Power
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Solution Overview
Problem
Higher order continuous time sigma delta (CT-SD) analog to digital converters (ADCs) face challenges in reducing inter-symbol interference (ISI) and increasing power consumption due to the need for additional components and complex feedback paths, which is particularly problematic in portable devices where space and power are limited.
Innovation Solution
The implementation of a shared current steering digital to analog converter (DAC) structure between adjacent integration stages in the modulator, eliminating the need for dedicated buffer amplifiers and reducing the number of components, thereby minimizing power consumption and area requirements while maintaining increased gain and reduced quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional integrator stages are added to increase the order of the CT-SD ADC, then gain is increased and quantization noise is attenuated, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the feedback amplifier of one integrator stage with the buffer amplifier of the adjacent integrator stage. Specifically, the feedback amplifier of the first integrator stage is shared as the buffer amplifier for the second integrator stage, and vice versa. This merging eliminates redundant components and reduces the overall complexity of the modulator while maintaining the required functionality of multiple integrator stages for quantization noise attenuation.
Solution Approach 2:
Each amplifier in the integrator stages is designed to perform multiple functions. The feedback amplifier of one stage simultaneously serves as the buffer amplifier for the adjacent stage. This multi-functionality reduces the total number of amplifiers needed in the modulator, thereby reducing device complexity and power consumption while still achieving the desired gain and quantization noise attenuation through multiple integration stages.
2Measurement precision
If additional integrator stages are added to increase the order of the CT-SD ADC, then gain is increased, but power consumption increases
Solution Approach 1:
The patent combines the feedback amplifier of one integrator stage with the buffer amplifier of the adjacent integrator stage into a single shared amplifier. This merging reduces the total number of active components that consume power. By sharing amplifiers between stages, the power consumption increases much less than it would with fully independent amplifiers for each stage, while still achieving the necessary gain through multiple integration stages.
Solution Approach 2:
The shared amplifiers are designed to perform multiple functions simultaneously - acting as feedback amplifiers for one stage and buffer amplifiers for adjacent stages. This multi-functionality ensures that the power-consuming components are minimized while still providing the required signal amplification and buffering functions across multiple integrator stages, thereby achieving high gain with controlled power consumption.
3Measurement precision
If additional integrator stages are added to increase the order of the CT-SD ADC, then quantization noise is attenuated, but area requirements increase
Solution Approach 1:
The patent merges the feedback amplifier of one integrator stage with the buffer amplifier of the adjacent integrator stage. This merging reduces the total number of amplifier circuits required in the modulator. Since amplifiers occupy significant area in integrated circuits, reducing their number directly reduces the overall modulator area while still maintaining multiple integrator stages for quantization noise attenuation.
Solution Approach 2:
The shared amplifiers serve multiple purposes - providing feedback for one integrator stage and buffering for adjacent stages. This multi-functionality reduces the component count and consequently the area required for the modulator. The design achieves the area reduction goal by making each amplifier do the work of what would traditionally require two separate amplifiers, while still supporting multiple integration stages for noise attenuation.
Data Source
AI summary
A continuous time sigma delta modulator for use in a continuous time sigma delta analog to digital converter is described. The modulator comprises a sequence of integration stages and a quantizer arranged to receive an output from the last integration stage in the sequence. Each integration stage comprises an integrator circuit that in turn comprises an amplifier and the sequence of integration stages comprises a pair of integration stages. The pair of integration stages further comprises a shared current steering DAC and wherein the amplifier in the integrator circuit in a first of the pair of integration stages forms part of a current steering circuit for the second of the pair of integration stages and the amplifier in the integrator circuit in the second of the pair of integration stages forms part of a current steering circuit for the first of the pair of integration stages.