Digital Sigma-Delta Modulator Memory Segmentation for Multi-Channel I/O
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Solution Overview
Problem
Conventional digital sigma-delta modulators require a large amount of hardware to process multiple inputs and outputs, limiting the reduction of hardware size due to the need for multiple memories, even when using multiplexers and demultiplexers.
Innovation Solution
Implementing a digital sigma-delta modulator with a multiplexer, an adder, a memory that divides data into A-bit and (N−A)-bit components, and a demultiplexer, where multiple N-bit memories are replaced by multiple A-bit memories and one (N−A)-bit memory, reducing memory capacity without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If M number of digital sigma-delta modulators are used to process M pairs of inputs and outputs simultaneously, then processing capability is improved, but hardware size increases
Solution Approach 1:
The patent combines M separate digital sigma-delta modulators into a single integrated modulator that processes M pairs of inputs and outputs simultaneously. The adder, memory, and control logic are shared across all M channels, reducing hardware size while maintaining processing capability for multiple input-output pairs.
Solution Approach 2:
The single digital sigma-delta modulator is designed to handle M different input signals and produce M different output signals through time-division multiplexing. The same adder, memory unit, and control circuitry are universally applied to all M channels, eliminating the need for dedicated hardware per channel.
2Area of stationary object
If multiplexers and demultiplexers are used to process multiple inputs and outputs with one SDM, then hardware size is reduced, but memory size remains large
Solution Approach 1:
The N-bit memory is segmented into multiple smaller memories: M number of first memories storing A-bit data each, and one second memory storing (N-A)-bit data. This segmentation reduces the memory size required per channel while maintaining the overall processing capability for M input-output pairs.
Solution Approach 2:
The patent introduces a new dimension of data organization by dividing the memory structure into multiple banks of smaller memories arranged in a two-dimensional array, rather than using a single large linear memory. This allows more efficient memory access and reduces the total memory capacity needed.
3Measurement precision
If N-bit memories are used in each digital sigma-delta modulator, then processing precision is maintained, but memory capacity increases
Solution Approach 1:
Different portions of the data are stored in memories of different sizes: the most significant A bits are stored in the first memories, while the remaining (N-A) bits are stored in the second memory. This local differentiation optimizes memory usage by storing only the necessary precision in each memory unit.
Solution Approach 2:
The patent changes the parameter of memory bit-depth from a uniform N bits across all channels to a differentiated structure with A bits in first memories and (N-A) bits in the second memory. This parameter change reduces total memory capacity while preserving processing precision through the feedback mechanism.
Data Source
AI summary
A digital sigma-delta modulator may be provided that includes: a multiplexer which receives N-bit input data from each of M number of input terminals and sequentially outputs; an adder which outputs carry out (CO) data and N-bit added data obtained by adding the N-bit input data and N-bit added data output in a previous cycle; a memory which divides the N-bit added data output from the adder into A-bit added data and (N−A)-bit added data and stores the A-bit added data and the (N−A)-bit added data; and a demultiplexer which receives the output carry out (CO) data and outputs to each of M number of output terminals.