Multiplexed Sigma-Delta ADC for Cycle-By-Cycle Channel Sampling
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Solution Overview
Problem
Sigma-delta analog-to-digital converter (ADC) circuits face challenges in multiplexing multiple channels due to slow memory flushing rates and inability to retain past data, which slows down the multiplexing rate and alters filtering actions in analog and digital decimation filters.
Innovation Solution
A multiplexed sigma-delta ADC circuit design that uses a shared analog circuit with a memoryless ADC and digital channels, allowing for cycle-by-cycle sampling of multiple channels by processing analog input signals through a digital-to-analog feedback loop, enabling dynamic multiplexing without altering filtering actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory flushing is performed in sigma-delta ADC to enable multiplexing between channels, then channel switching capability is improved, but sampling speed deteriorates due to slow memory flushing rate
Solution Approach 1:
The patent segments the ADC system into multiple independent parallel ADC circuits, each capable of processing one channel. This eliminates the need for memory flushing when switching channels, as each ADC maintains its own independent data path and processing pipeline, thereby preserving high sampling speed while enabling multi-channel operation.
Solution Approach 2:
The patent implements a shared digital signal processing unit that serves all ADC circuits. This universal resource handles the decimation filtering and digital signal processing for multiple channels simultaneously, reducing overall system complexity and area while maintaining high sampling rates across all channels.
2Loss of information
If analog loop filter circuits retain past data for multiplexing, then historical information is preserved, but leakage effects prevent reliable storage
Solution Approach 1:
The patent replaces the analog loop filter circuit with a digital filter implemented in the digital domain. This substitution eliminates leakage effects inherent in analog integrators, as digital systems can perfectly retain historical data without degradation. The digital filter processes incoming data while maintaining accurate running averages and historical information for all channels.
3Adaptability or versatility
If samples are skipped in digital decimation filter for multiplexing, then channel switching is enabled, but filtering action is altered
Solution Approach 1:
The patent provides each ADC circuit with its own dedicated digital decimation filter, ensuring that filtering operations for each channel are completely independent. This segmentation prevents any channel switching or sample skipping from affecting the filtering precision of other channels, as each filter processes its channel's data stream continuously without interruption.
Solution Approach 2:
The patent performs channel selection and signal routing before the data enters the decimation filter. By establishing the correct data path in advance and ensuring continuous sample flow to each filter, the system maintains uninterrupted filtering action for all channels, preserving filtering precision while enabling simultaneous multi-channel operation.
4Area of stationary object
If shared analog circuit is used for multiple channels, then area is reduced, but multiplexing speed is slowed by memory flushing requirements
Solution Approach 1:
The patent segments the analog conversion function across multiple parallel ADC circuits rather than using a single shared ADC with multiplexing. This approach increases the analog circuit area but eliminates the multiplexing bottleneck, as each ADC operates independently at full speed. The shared resources are confined to the digital domain where high-speed parallel processing is feasible.
Solution Approach 2:
The patent transitions from time-division multiplexing (single ADC serving multiple channels sequentially) to spatial parallelism (multiple ADCs serving multiple channels simultaneously). This dimensional change from sequential to parallel architecture resolves the fundamental speed limitation imposed by memory flushing requirements in time-division systems.
Data Source
AI summary
A sigma-delta ADC circuit with an analog loop filter circuit can be multiplexed between different inputs by flushing the memory of the analog loop filter integrators and the digital decimation filter and filling it with new data for the current input. However, filling the memory can be slow with respect to the sampling frequency because the information about past history has to be built up before meaningful output data can be generated. Thus, the multiplexing rate between channels using a sigma-delta ADC circuit can be slowed by such memory flushing. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques can provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and that can multiplex over a number of channels dynamically.