SAR Quantizer Noise Shaping for Lower-Delay CT Sigma-Delta Modulators

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Solution Overview

Problem

Continuous-time sigma-delta modulators face challenges in achieving high performance while maintaining low cost and reducing circuit size and critical path delay, particularly due to the complexity of digital-to-analog converters (DACs) when using multi-bit quantizers.

Innovation Solution

A bit-reducing noise-shaping successive approximation register (SAR) quantizer and continuous-time sigma-delta modulator (CTSDM) design that includes an SAR highly-significant-bit switch circuit, lowly-significant-bit switch circuit, comparing circuit, and control circuits to generate digital output signals, reducing the demand for circuit area and lowering critical path delay through noise-shaping operations and DAC MSB-only Randomization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a multi-bit quantizer of higher resolution is used in CTSDM, then performance is improved, but DAC design complexity increases

Engineering Contradiction:

Improvequantizer resolutionVSAvoidDAC design complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the quantizer into two parts: a noise-shaping quantizer (NSQ) that generates high-resolution digital output, and a separate DAC that converts only the most significant bits to analog signal. This segmentation allows the NSQ to achieve high resolution while the DAC operates with reduced complexity, processing fewer bits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary digital signal processing stage between the quantizer and DAC. The NSQ produces a high-resolution digital signal, which is then processed through bit-reducing noise-shaping logic before being converted to analog by the DAC. This intermediary stage separates the resolution generation from the analog conversion, reducing DAC complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If DAC uses calibration technique, then performance is improved at certain conditions, but performance varies across different chips and conditions

Engineering Contradiction:

ImproveDAC performance consistencyVSAvoidperformance across different chips and temperatures

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent extracts the calibration requirement from the DAC by reducing the number of bits the DAC must process. Since the DAC only converts the most significant bits while the noise-shaping quantizer handles the less significant bits digitally, the DAC's sensitivity to calibration variations is reduced, improving consistency across different chips and operating conditions.

Inventive Principle:

Principle #2Taking out (Extraction)

3Measurement precision

If DAC is designed to fulfill the dynamic range of ADC, then dynamic range is achieved, but circuit size becomes large

Engineering Contradiction:

Improvedynamic rangeVSAvoidDAC circuit size

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the bit processing function, where the noise-shaping quantizer generates high-resolution digital signals and the DAC processes only the most significant bits. This segmentation allows the system to achieve the full dynamic range through the combined digital processing of the NSQ and the reduced-bit DAC, significantly reducing the DAC circuit size compared to a full-resolution DAC.

Inventive Principle:

Principle #1Segmentation

4Manufacturing precision

If DEM technique is used in DAC, then linearity is improved, but critical path delay increases

Engineering Contradiction:

ImproveDAC linearityVSAvoidcritical path delay

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the quantizer and DAC operations in time, using a successive approximation approach where the NSQ generates digital output bits sequentially from most significant to least significant. This temporal segmentation allows the DAC to process each bit sequentially rather than simultaneously, reducing the critical path delay while maintaining linearity through the noise-shaping process.

Inventive Principle:

Principle #1Segmentation

5Productivity

If digital delta-sigma truncator technique is used, then bit reduction is achieved, but total delay becomes too long

Engineering Contradiction:

Improvebit reduction efficiencyVSAvoidtotal delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary noise-shaping and bit reduction in the digital domain before the analog conversion stage. The noise-shaping quantizer pre-processes the signal to shape quantization noise to higher frequencies, and the bit-reducing logic prepares the digital signal in advance, allowing the DAC to operate with reduced bits and reduced delay compared to post-conversion processing approaches.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10498353B2Successive approximation register quantizer and continuous-time sigma-delta modulator

Publication Date: 2019.12.03 REALTEK SEMICON CORP

AI summary

Disclosed is a successive approximation register (SAR) quantizer and a continuous-time sigma-delta modulator (CTSDM) using the SAR quantizer. The SAR quantizer is capable of generating M highly-significant bits as a digital output signal, and generating L lowly-significant bit(s) for the execution of noise shaping operation. Therefore, the SAR quantizer and the CTSDM can reduce the demand for the circuit area of a digital-to-analog converter and lower the delay of a critical path, so as to improve the performance and cut the cost.