Resolver Signal Processing With Fine Time Quantization
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Solution Overview
Problem
Existing methods for processing analog measured-value signals in resolver systems suffer from rough time quantization, limiting synchronization quality between primary and secondary control loops, as they require large time increments for measuring duration adjustments, which restricts the precision of synchronization and data accuracy.
Innovation Solution
A method that allows for high-time-resolution definition of the measuring interval by using a delta-sigma modulator with a series of integrators and a second digital filter that calculates differences between intermediate data words at specific time intervals, enabling precise analog-to-digital conversion and eliminating the need for differentiators and decimation filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delta-sigma modulator with a Sinc3 filter and decimation filter is used for analog-digital conversion, then the filter effect is sufficient, but the time quantization becomes rough (TD must be substantially greater than TS)
Solution Approach 1:
The patent segments the filtering function into multiple independent first-order Sinc filters operating in parallel, each handling a portion of the frequency spectrum. This allows the system to achieve the required filter effect through parallel processing at the high sampling rate TS, avoiding the need for a single complex filter that would require reduced sampling rate TD, thereby maintaining fine time quantization resolution.
Solution Approach 2:
The patent transitions from a single-dimensional sequential filtering approach (one complex filter at reduced rate) to a multi-dimensional parallel processing architecture. Multiple simple filters operate simultaneously at the original high sampling rate, effectively adding a parallel processing dimension that resolves the contradiction between filter complexity and time resolution.
2Measurement precision
If the period duration of the sampling interval is modified for synchronization, then the synchronization quality improves, but the achievable precision is limited by rough time quantization TD
Solution Approach 1:
The patent changes the fundamental parameter of sampling rate from the reduced rate fD to the original high rate fS. By maintaining operation at the high sampling rate TS throughout the processing chain, the system enables synchronization adjustments in fine time increments rather than being constrained to coarse TD multiples, directly improving synchronization precision.
3Quantity of substance
If three accumulators operating at frequency FS are followed by three differentiators operating at frequency FD, then the integration function is achieved, but the output signal is only available at rough time quantization TD
Solution Approach 1:
The patent extracts and removes the differentiator stage from the signal processing chain. By eliminating the frequency conversion from FS to FD through differentiators, the system maintains the high sampling rate TS throughout, preventing the loss of time resolution that occurs when signals are downsampled to the coarser TD grid.
Solution Approach 2:
Instead of the conventional approach of integrating at high rate then differentiating to reduce rate, the patent inverts the logic by maintaining the high sampling rate throughout and achieving the required integration function through parallel accumulators operating at FS, thereby avoiding the time resolution loss inherent in the traditional high-to-low rate conversion approach.
Data Source
AI summary
In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.