Current-Mode Sigma-Delta ADC with Parallel Loops for Excess Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed continuous-time sigma-delta ADCs face instability and reduced resolution due to excess loop delay, which is exacerbated by the need for power-hungry pre-amplifiers with high gain bandwidth requirements, leading to undesirable delays and power consumption.
Innovation Solution
A current-mode multi-path excess loop delay compensation technique is introduced, eliminating the need for pre-amplifiers by duplicating summation nodes and using multiple fast feedback loops operating in the current domain, with transconductance amplifiers and current-steering DACs to directly drive comparators, thereby reducing delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-amplifiers with high gain bandwidth are used to compensate excess loop delay, then stability and resolution are improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the pre-amplifier stage from the conventional SDM architecture. By eliminating this power-hungry component, the invention resolves the contradiction between achieving stability through delay compensation and maintaining low power consumption. The excess loop delay is compensated through alternative means that do not require high-power pre-amplifiers.
Solution Approach 2:
The invention changes the operating parameters of the SDM by operating in the current domain rather than voltage domain. This parameter change allows the system to achieve the same stability and resolution performance without requiring the high gain bandwidth that would necessitate power-hungry pre-amplifiers.
2Measurement precision
If pre-amplifiers with high gain bandwidth are used to reduce delay, then resolution is improved, but power consumption increases
Solution Approach 1:
The patent removes the pre-amplifier stage that consumes excessive power. By extracting this component and implementing delay compensation through other means (current-domain operation), the invention maintains high resolution while eliminating the power consumption penalty associated with high gain bandwidth pre-amplifiers.
Solution Approach 2:
The invention substitutes the voltage-domain pre-amplifier system with a current-domain operation system. This substitution eliminates the need for power-hungry amplifiers while maintaining the resolution performance through direct current-mode signal processing and excess loop delay compensation.
3Device complexity
If conventional voltage-domain operation is used, then design is simpler, but delay and power consumption increase
Solution Approach 1:
The patent changes the fundamental operating domain from voltage to current. This parameter change enables the system to reduce delay by operating in the current domain, which allows for faster signal processing and direct driving of comparators without the need for intermediate voltage amplification stages.
Data Source
AI summary
A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.