Multiple-Feedback ADC for Noise-Shaped High-Resolution Conversion
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Solution Overview
Problem
Conventional analog-digital converters face limitations in achieving high resolution without increasing comparator noise, especially when operating at high speeds, due to the need for high internal clock frequencies and wide bandwidth comparators.
Innovation Solution
The proposed analog-digital converter employs a multiple feedback structure with a capacitor digital-analog converter and a delta sigma analog-digital converter, using switches and capacitors to generate residue voltages and integrate them, allowing for noise shaping and reducing comparator noise through feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional analog-digital converters operate at high speeds, then conversion speed is improved, but comparator noise increases
Solution Approach 1:
The patent segments the conversion process into multiple stages: a first analog-digital converter operating at Nyquist rate generates a first digital output signal, while a second analog-digital converter (delta-sigma type) operates at oversampling frequency to generate a second digital output signal. These segmented conversion paths allow each converter to operate at optimized speeds, preventing the need for a single high-speed converter that would generate excessive comparator noise.
Solution Approach 2:
The patent implements feedback mechanisms where the first digital output signal is fed back to the capacitor digital-analog converter, and the second digital output signal is fed back to the delta-sigma analog-digital converter. This feedback allows for error correction and noise shaping, enabling high-resolution conversion without requiring high-speed comparators that would generate excessive noise.
2Measurement precision
If high resolution is achieved in conventional analog-digital converters, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the high-resolution conversion task into two separate converters: a first analog-digital converter handling the main conversion at Nyquist rate, and a second delta-sigma analog-digital converter handling oversampling and noise shaping. This segmentation allows each converter to be simpler in design while collectively achieving high resolution, avoiding the need for a single complex high-resolution converter.
Solution Approach 2:
The patent employs periodic oversampling in the delta-sigma converter, where multiple samples are taken at a frequency higher than Nyquist rate. This periodic action distributes the conversion workload over time, allowing lower-resolution individual comparisons to accumulate into high-resolution output through averaging and noise shaping, thereby reducing the complexity of individual comparator circuits.
3Productivity
If Nyquist rate conversion is implemented, then productivity is improved, but comparator noise restrictions become more limiting
Solution Approach 1:
The patent segments the conversion system so that the first analog-digital converter operates at Nyquist rate to maintain high productivity, while the second delta-sigma converter operates at oversampling frequency to handle noise shaping. This segmentation allows the Nyquist-rate converter to achieve high conversion efficiency without being constrained by comparator noise issues, as the noise management is delegated to the separate oversampling converter.
Solution Approach 2:
The patent introduces a capacitor digital-analog converter as an intermediary element that receives the first digital output signal and generates a feedback signal. This intermediary facilitates the interaction between the two converters, allowing the Nyquist-rate converter to operate efficiently while the intermediary handles the noise-shaping feedback, thus separating the productivity function from the noise management function.
Data Source
AI summary
An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval, wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors. The analog-digital converter may be included in various electronic devices, including communication devices.