Non-Switched Capacitor Integrators for Stable Delta-Sigma ADCs
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Solution Overview
Problem
High-order delta-sigma analog-to-digital converters require additional circuitry for stability, which increases complexity and power consumption, as they need feedback or feedforward topologies to introduce zeros in the transfer function.
Innovation Solution
The implementation of non-switched capacitor circuits in delta-sigma converters provides feed-forward loop stability without adding substantial complexity, using a cascade of fully-differential switched-capacitor delayless and delayed integrators with non-switched capacitors to introduce zeros inside the unit circle, thereby stabilizing the loop without additional analog summing circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If feedback or feedforward topologies are used to stabilize high-order delta-sigma converters, then loop stability is improved, but device complexity increases due to additional D/A converters or operational amplifiers
Solution Approach 1:
The patent extracts the stability-providing function from traditional feedback/feedforward topologies and implements it through a feedforward path that directly sums the quantized output with the analog input. This eliminates the need for additional D/A converters or operational amplifiers while maintaining loop stability through the strategic placement of zeros in the transfer function.
Solution Approach 2:
The existing summing node in the delta-sigma converter is made multi-functional by adding the feedforward path. This single node now performs both the traditional feedback summing and the feedforward addition, eliminating the need for separate summing circuits and reducing overall device complexity while maintaining stability.
2Stability of the object's composition
If additional circuitry is added to provide zeros in the transfer function for stability, then loop stability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming additional D/A converters and operational amplifiers from the circuit by extracting the stability function and implementing it through a simplified feedforward path that utilizes existing circuit components, thereby reducing power consumption while maintaining loop stability.
3Measurement precision
If higher-order delta-sigma converters are used to achieve high SNR at low OSR, then measurement precision is improved, but device complexity increases due to stability requirements
Solution Approach 1:
The patent extracts the stability-providing mechanism from complex feedback/feedforward topologies and implements it through a streamlined feedforward path. This allows higher-order converters to achieve high SNR at low OSR without the circuit complexity and power consumption associated with traditional stability compensation methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances loop stability and reduces phase errors in discrete-time integration, allowing for higher-order noise shaping without increasing circuit complexity or power consumption, while maintaining high signal-to-noise ratio at low oversampling ratios.
Implementation Method 1
High order delta-sigma A/D converters are desirable because they provide high SNR at a low OSR, but they must be stabilized by at least one zero in the transfer function. Prior art delta-sigma converters employ feedback or feedforward topologies to provide the zeros
Implementation Method 2
during the integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor
Data Source
AI summary
Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.