ADC Reference Path Reconfiguration for Mismatch Distortion Reduction
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Solution Overview
Problem
Existing data conversion circuits, such as ADCs, suffer from harmonic distortion due to element mismatch, leading to intermodulation distortion products that can cause false targets in radar systems and other applications, and current dynamic element matching techniques increase semiconductor die area, power consumption, and noise generation.
Innovation Solution
The method involves adding dither to the reference path of a sigma-delta ADC by swapping comparator references, which randomizes comparator offsets and DAC element mismatches, reducing deterministic quantization error and distortion without increasing die area, power, or stability concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic element matching techniques are used to reduce element mismatch, then harmonic distortion is reduced, but semiconductor die area increases
Solution Approach 1:
The patent changes the timing parameter of reference signal application by introducing dithered delay values. Different comparators receive reference signals with different programmable delays, which randomizes the effective sampling instant and averages out mismatch effects without requiring additional circuit elements or increasing die area.
2Measurement precision
If dynamic element matching techniques are used to reduce element mismatch, then harmonic distortion is reduced, but power consumption increases
Solution Approach 1:
The patent uses the existing reference signal distribution network and comparator structure to achieve mismatch compensation. The system serves itself by utilizing the inherent timing variations and programmable delay elements already present in the architecture, avoiding the need for additional active compensation circuits that would consume extra power.
3Measurement precision
If dynamic element matching techniques are used to reduce element mismatch, then harmonic distortion is reduced, but noise generation increases
Solution Approach 1:
The patent converts the potentially harmful effect of timing variations and element mismatches into a beneficial randomization mechanism. By intentionally introducing dithered delays that randomize the sampling instants, the deterministic mismatch errors are transformed into randomized noise that can be filtered or averaged, effectively converting a harm into a benefit.
4Measurement precision
If dynamic element matching techniques are used to reduce element mismatch, then harmonic distortion is reduced, but loop delay increases causing stability concerns
Solution Approach 1:
The patent applies timing adjustments and dithered delays to the reference signals before they reach the comparators. This preliminary randomization of sampling instants occurs in advance of the main conversion process, allowing mismatch effects to be averaged out without introducing additional delay loops or feedback paths that would increase overall loop delay and threaten stability.
Data Source
AI summary
An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.