Delta-Sigma ADC PGA Gain Calibration Without External References
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Solution Overview
Problem
Analog-to-digital converters (ADCs) with programmable gain amplifier (PGA) gain input stages face challenges in gain error calibration due to the need for accurate reference voltages, which may not be available in all electronic devices, and the slow testing process required for each gain permutation, leading to long settling times.
Innovation Solution
The proposed solution includes an ADC with a buffer circuit and multiplexer that uses a variable resistor with individually selectable resistive branches to calibrate gain errors without requiring external reference voltages, allowing for efficient determination and correction of gain errors through control logic that routes inputs and enables resistive branches to achieve desired gain values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional gain error testing is performed using accurate reference voltages, then measurement precision is improved, but device complexity increases and ease of operation deteriorates due to requiring external reference voltage sources
Solution Approach 1:
The ADC performs self-calibration by using its own output code as the reference for gain error determination. The control logic routes the ADC output back to the buffer circuit input, creating a self-referencing calibration loop that eliminates the need for external reference voltage sources while maintaining measurement accuracy
Solution Approach 2:
The buffer circuit is designed to perform multiple functions: normal signal buffering during ADC operation and self-calibration reference during gain error correction. The same buffer circuit handles both the ADC output signal and the reference voltage that would traditionally come from an external source, reducing overall system complexity
2Measurement precision
If each gain permutation is tested individually with long settling time, then measurement precision is improved, but productivity deteriorates due to slow testing process
Solution Approach 1:
The buffer circuit is pre-configured with selectable gain settings through the variable resistor network before calibration begins. The control logic determines the appropriate gain configuration in advance and prepares the corresponding resistive branches, allowing the calibration to proceed without delays for settling or reconfiguration during the measurement process
Solution Approach 2:
The variable resistor with individually selectable resistive branches allows dynamic adjustment of the buffer circuit gain during calibration. The control logic can quickly switch between different gain configurations by enabling or disabling specific resistive branches, eliminating the need for slow mechanical adjustments or external component changes
3Measurement precision
If external reference voltage sources are used for calibration, then measurement precision is improved, but device complexity increases due to additional external components
Solution Approach 1:
The calibration reference function is extracted from the external domain and relocated to the ADC internal circuitry. The ADC output code serves as the reference voltage source, eliminating the need for external reference voltage generators and simplifying the overall system architecture
Solution Approach 2:
The calibration function is merged with the normal ADC operation circuitry. The buffer circuit, variable resistor, and control logic work together to provide both signal buffering and self-calibration functions, reducing the need for separate calibration components and external equipment
Data Source
AI summary
An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.