Analogue Conversion TRIZ Cases

Dual feedback paths let a class-D amplifier switch modes and calibrate analogue-path DC offset to cut distortion without pops or clicks.

A capacitive element adds a higher-frequency pole so a telescopic cascode OTA meets timing with lower power and stable phase margin.

Delta-sigma bit streams enable real-time monitoring of power electronic assemblies for early fault detection and service life prediction.

Separate PMOS and NMOS gate coupling and biasing cuts ADC quantizer current while improving settling speed across PVT variations.

Delta-sigma digitization virtualizes optical transmission to separate noise from signal and support higher-order modulation in HFC links.

A dither-based counting approach exposes ADC sampler and amplifier nonlinearity in the digital domain, cutting power use and speeding calibration.

Oversampled noise-shaped digitization carries multiple RAT carriers with higher spectral efficiency while simplifying remote radio heads.

A two-mode delta-sigma readout speeds thermopile pixel digitization while suppressing noise and limiting crosstalk.

A single-bit stream crosses the isolator without separate sync lines, cutting latency, interference sensitivity, and ADC link complexity.

Separating weight sign from magnitude lets a memristor dot product engine cut ADC precision by one bit while preserving accuracy and parallelism.

Samples input and reference voltages in phases to preserve ADC resolution, cut power use, and relax control-signal timing.

Node-voltage detection adapts the sigma-delta loop to suppress blocker signals, improving conversion stability with lower power use.

A shared first-block amplifier replaces a high-gain second stage across ΔΣ, cyclic, and hybrid modes to cut current draw and chip area.

Self-referencing ADC calibration uses selectable resistor branches to measure and correct PGA gain error without external reference voltages.

Multi-stage noise shaping and digital cancellation suppress quantization error and mismatch effects in high-speed, high-resolution ADCs.

A digital copy of the feedback DAC models unit mismatch in a sigma-delta ADC, correcting non-linearity and preserving SNR gains.

Cross-correlation with injected LFSR sequences lets CT MASH ADCs track transfer errors and cut quantization noise leakage for better SNR.

Voltage-following sigma-delta circuits sample self, mutual, and pen touch signals at once, cutting noise and integration time on large displays.

Matching the ripple reduction loop to the sampling frequency suppresses noise peaking and preserves delta-sigma modulator stability.

A shared ADC uses temperature-mode digital coefficients to preserve sensor accuracy while reducing circuit area and power consumption.

Control-signal intervals set the oversampling ratio in a delta-sigma ADC, avoiding extra terminals while balancing S/N ratio and output rate.

An op-amp-less delta-sigma potentiostat helps implantable CMOS dies cut power use while keeping fast, low-noise electrochemical imaging.

A differential single-node driver cuts parasitic capacitance and noise, speeding touch location detection on large projected capacitive sensors.

Simultaneous multi-frequency sensing cuts touch sample time while improving noise rejection for self, mutual, and pen channels.

A one-sample delayed DAC feedback path simplifies quantization noise coupling in delta-sigma ADCs while preserving SNQR gains.

Chopping and delta-sigma conversion improve low-frequency sensor resolution while suppressing noise and reducing power for compact sensors.

Matched digital filtering cancels VCO quantizer error in a pipelined ADC, improving SNR and bandwidth without higher-order loop power.

Switchable gain phases and matched counter steps cut sigma-delta ADC clock cycles, lowering power use while preserving conversion accuracy.

By settling the buffer and residue amplifier at the same time, this multi-stage ADC approach shortens offset cancellation and lowers power use.

By sharing a capacitor and amplifier between sample-and-hold and integrator stages, this delta-sigma ADC cuts chip area without losing conversion effectiveness.

Direct RF digitization with bandpass delta-sigma ADCs cuts receiver power and noise by using digital IQ generation and resonant filtering.

By separating carrier and signal paths, this amplifier cuts DAC noise and improves stability in power-efficient audio output stages.

Non-recursive residue calculation lets a digital delta-sigma modulator scale sample rate through parallelization and pipelining without spectral artifacts.

Near-zero asymmetric quantization and active sigma biasing suppress limit-cycle noise peaks while keeping the output noise floor low.

PI amplitude control with integrator reset cuts steady-state error and stabilizes digital resonance drive in Coriolis flowmeters.

A dual-input resonator converts tiny sensor current changes into digital output with oversampling, cutting modulator power, area, and complexity.

Parallel sensor signal combining with feedback-tuned weighting cuts scanning latency and improves signal-to-noise ratio in high-speed position measurement.

Active ladder networks distribute gain cells and reactive segments to shape noise over wide bandwidths without weakening the desired signal.

A DAC feedback loop stabilizes LED current in TOF illumination drivers, cutting phase noise, flicker, and parasitic capacitance effects.

Signal-level detection adjusts transistor gate bias in a capacitive D/A converter to cut power use while maintaining low distortion.

A locked static fault state and output change monitoring let one pulse density transmission path carry analog data while detecting missing dynamics.

Simultaneous sigma-delta sampling of self, mutual, and pen capacitance improves touch speed, sensitivity, and noise rejection on large displays.

Differently delayed quantizer feedback suppresses metastability in sigma-delta control loops while preserving phase margin and bandwidth.

Sigma-delta touch sensing enables simultaneous self, mutual, and pen sampling while reducing parasitic capacitance noise on large displays.

A modulus subtractor and polyphase decimation filter simplify differential ring-oscillator ADC conversion while cutting circuit area and power.

Split pMOSFET and nMOSFET DAC paths use tailored bulk and gate voltage levels to cut body effect, ON resistance, and circuit area.

An extended Barker code added inside the modulator loop decorrelates idle tones and cuts intermodulation products for low input signals.

A delta-sigma modulator and digital filter shrink the input receiver AFE while maintaining fast, low-power processing of sensor electrode signals.

A compound switch delays a smaller parallel switch so charge injection goes to the output, cutting integrator offset without slower settling or tones.

Variable ADC clocking spreads noise frequency and stabilizes output signals, improving sampling accuracy without a fixed-frequency limit.