Multi-Stage ADC Offset Cancellation Through Overlapped Settling

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Solution Overview

Problem

Multi-stage analog-to-digital converters (ADC) circuits face inefficiencies due to the sequential settling time of signal conditioning circuits and residue amplifiers during offset cancellation, which prolongs the conversion time and increases power consumption.

Innovation Solution

The proposed technique combines the settling time of signal conditioning circuits and residue amplifiers by allowing them to settle concurrently, reducing the overall conversion time by canceling the offset and amplifying the residue simultaneously within the ADC circuit stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If offset cancellation is performed sequentially by signal conditioning circuit and residue amplifier, then offset is eliminated, but conversion time increases

Engineering Contradiction:

Improveoffset cancellation accuracyVSAvoidconversion time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges the offset cancellation operations of the signal conditioning circuit and residue amplifier into a single concurrent process. The signal conditioning circuit performs offset cancellation on the input signal while the residue amplifier simultaneously performs offset cancellation on the residue signal, eliminating sequential delays and reducing total conversion time while maintaining precision.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If sequential settling is used for signal conditioning circuit and residue amplifier, then stable output is achieved, but power consumption increases

Engineering Contradiction:

Improveoutput stabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements continuous concurrent operation where the signal conditioning circuit and residue amplifier both perform their offset cancellation and signal processing functions simultaneously throughout the conversion period. This eliminates idle waiting time and reduces the total duration power is consumed, thereby reducing overall power consumption while maintaining output stability through continuous monitoring and adjustment.

Inventive Principle:

Principle #20Continuity of useful action

3Speed

If concurrent settling and amplification are performed, then conversion speed increases, but circuit complexity increases

Engineering Contradiction:

Improveconversion speedVSAvoidcircuit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent designs the signal conditioning circuit and residue amplifier to perform multiple functions simultaneously: offset cancellation, signal amplification, and residue generation all occur in parallel within the same circuit blocks. This multi-functionality approach achieves high conversion speed without proportionally increasing circuit complexity, as the same hardware components execute multiple operations concurrently rather than requiring separate dedicated circuits for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10868554B1Time-efficient offset cancellation for multi-stage converters

Publication Date: 2020.12.15 ANALOG DEVICES INT UNLTD CO

AI summary

Techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques can allow the signal conditioning circuit and the residue amplifier to settle together.