Switched-Capacitor Integrator Switching Scheme for Low Offset
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Solution Overview
Problem
Switched-capacitor integrators face a trade-off between offset contribution from charge injection mismatch and settling time, with existing methods either trading settling time or introducing tones that require post-processing to mitigate.
Innovation Solution
A switching scheme is introduced that uses a compound switch with a smaller switch in parallel to the main switch, where the smaller switch opens only after the main switch, ensuring all charge injection is integrated, thereby reducing the net offset without impacting settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional single switch is used in switched-capacitor integrator, then device complexity is low, but offset contribution from charge injection mismatch increases
Solution Approach 1:
The single switch is segmented into multiple parallel switches (first switch, second switch, third switch, fourth switch) with different widths. Each switch handles a portion of the charge injection, and their combined effect reduces the net offset contribution while maintaining the overall switching function. This segmentation allows the charge injection mismatches to partially cancel each other out.
Solution Approach 2:
Each switch in the parallel combination is assigned a different width (W1, W2, W3, W4), creating local quality differences. This non-uniform distribution of switch widths optimizes the charge injection characteristics at each location, allowing the system to achieve lower overall offset by exploiting the spatial variation in switch properties.
2Measurement precision
If switch size is increased to reduce charge injection mismatch, then offset is reduced, but settling time increases
Solution Approach 1:
Instead of using a single large switch that would increase settling time, the solution segments the switching function across multiple smaller parallel switches. The combined conductance of these switches matches or exceeds that of a single large switch, maintaining fast settling, while the distributed charge injection reduces offset accumulation.
Solution Approach 2:
The parallel switch configuration uses asymmetric widths (W1≠W2≠W3≠W4) to optimize performance. This asymmetric design allows each switch to contribute differently to the total conductance and charge injection, achieving a balance between fast settling (high total conductance) and low offset (distributed charge injection).
3Measurement precision
If existing offset mitigation methods are used, then offset is reduced, but undesired tones are introduced requiring post-processing
Solution Approach 1:
The patent converts the potentially harmful charge injection effect into a beneficial cancellation mechanism. By carefully designing the parallel switch configuration, the charge injections from individual switches, which would normally be harmful, are made to cancel each other out, reducing net offset without requiring additional correction circuits that would introduce tones.
Data Source
AI summary
A switched-capacitor integrator is described having the contribution to offset from the charge injection mismatch of switches connected to the summing nodes mitigated by using a switching scheme that conveys basically all the charge injection to the output, thus preventing net offset from being integrated.