Ring-Oscillator ADC Decimation for Lower-Power Phase Conversion
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Solution Overview
Problem
The complexity and high power consumption of ring-oscillator based analog-to-digital converters (ADCs) due to the need for additional processing circuits and high-frequency sampling clocks, which complicates the conversion of analog signals into digital codes.
Innovation Solution
The integration of a polyphase decimation filter that merges the differentiator used in each ring-oscillator ADC with the first integrator in a conventional sinc decimation filter, and the implementation of a modulus subtractor to combine phase signals, reducing the need for complex digital circuitry and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional processing circuits are added to extend the range of the ring oscillator, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent combines the range extending logic circuit with the encoder to form a unified circuit that performs both functions. The encoder is modified to directly incorporate range extension capabilities, eliminating the need for separate processing circuits and reducing overall device complexity while maintaining extended measurement precision.
Solution Approach 2:
The encoder is designed to perform multiple functions: it encodes the phase information and simultaneously extends the measurement range. This multi-functional design eliminates the need for separate range extending logic circuits, reducing device complexity while maintaining the ability to measure across an extended range with high precision.
2Productivity
If a high frequency sampling clock is used, then the productivity is improved, but the use of energy increases
Solution Approach 1:
The patent employs periodic sampling at optimized intervals rather than continuous high-frequency sampling. The sampling clock is synchronized with the ring oscillator period, allowing accurate phase measurement at lower effective sampling rates. This periodic action maintains productivity by capturing essential signal information while significantly reducing the energy consumption associated with high-frequency clock operation.
Solution Approach 2:
The patent changes the sampling strategy from fixed high-frequency sampling to adaptive sampling based on the ring oscillator's operating conditions. By adjusting the sampling clock frequency to match the oscillator period and using phase-difference measurement techniques, the system achieves high productivity with reduced energy consumption compared to constant high-frequency sampling.
3Measurement precision
If additional digital circuits are added for decimation, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent integrates the decimation function into the existing encoder and phase detection circuits rather than adding separate decimation stages. The encoder is designed to directly output decimated digital codes by counting phase differences over multiple oscillator periods, combining measurement and decimation functions in a single circuit block to reduce overall device complexity.
Solution Approach 2:
The ring oscillator-based phase detector inherently performs the decimation function through its operation. By measuring the phase difference between successive oscillations and accumulating these differences, the system automatically achieves frequency division and decimation without requiring external digital decimation circuits, thereby maintaining measurement precision while reducing device complexity.
Data Source
AI summary
In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.