DAC Circuit Bulk Biasing for Lower ON Resistance and Area
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Solution Overview
Problem
Conventional digital to analog conversion (DAC) circuits utilize an equal number of P-type and N-type metal oxide semiconductor field effect transistors (MOSFETs), leading to large area occupation, significant body effects, and high ON resistances due to bulk terminal voltage configurations, making it difficult for MOSFETs to conduct effectively.
Innovation Solution
The proposed DAC device employs two separate DAC circuits with P-type and N-type MOSFETs, each receiving bulk voltages and gate signals with varying magnitudes to optimize voltage ranges, reducing the number of MOSFETs and minimizing body effects, allowing for efficient digital to analog conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional DAC circuit uses an equal number of pMOSFETs and nMOSFETs, then the circuit can achieve basic digital to analog conversion function, but the total number of MOSFETs becomes large and occupies large area
Solution Approach 1:
The patent divides the voltage range into two separate ranges: first voltage range (higher magnitude) and second voltage range (lower magnitude). Different DAC circuits are used for different voltage ranges, with the first DAC circuit handling higher voltages and the second DAC circuit handling lower voltages. This segmentation allows optimization of MOSFET usage in each range, reducing the total number of MOSFETs required while maintaining conversion accuracy.
Solution Approach 2:
The patent applies different bulk voltage configurations to different MOSFETs based on their operating requirements. For pMOSFETs handling first input voltages, bulk terminals receive first bulk voltages with magnitudes greater than the maximum first input voltage. For nMOSFETs handling second input voltages, bulk terminals receive second bulk voltages with magnitudes less than the minimum second input voltage. This localized optimization reduces body effects and improves conductivity in each specific operating region.
2Device complexity
If all bulk terminals of pMOSFETs receive the most positive voltage and all bulk terminals of nMOSFETs receive the most negative voltage, then the circuit configuration is simple, but significant body effects and large ON resistances occur
Solution Approach 1:
The patent changes the bulk voltage parameters dynamically based on the input voltage range. Instead of using fixed most positive and most negative voltages for all bulk terminals, the patent uses first bulk voltages with magnitudes greater than maximum first input voltages for pMOSFETs, and second bulk voltages with magnitudes less than minimum second input voltages for nMOSFETs. This parameter optimization minimizes body effects and reduces ON resistances, significantly improving MOSFET conductivity.
3Measurement precision
If the MOSFET is to transmit a voltage with magnitude approximately equal to the voltage magnitude of the signal at its gate terminal, then the conversion accuracy is maintained, but it becomes hard for the MOSFET to conduct
Solution Approach 1:
The patent creates different operating conditions for MOSFETs based on the voltage range they handle. For first DAC portions handling higher voltages, pMOSFETs receive first bulk voltages optimized for that range. For second DAC portions handling lower voltages, nMOSFETs receive second bulk voltages optimized for that range. This localized optimization ensures that each MOSFET operates in its optimal conduction region, maintaining both accuracy and conductivity.
Solution Approach 2:
The patent changes the bulk voltage parameters to create adequate voltage margins between the gate terminal voltage and bulk terminal voltage. By setting first bulk voltages with magnitudes greater than maximum first input voltages and second bulk voltages with magnitudes less than minimum second input voltages, the patent ensures MOSFETs operate with sufficient voltage headroom, making it easier for them to conduct while maintaining transmission accuracy.
4Area of stationary object
If separate DAC circuits are used for different voltage ranges, then the number of MOSFETs is reduced and area is minimized, but the circuit structure becomes more complex
Solution Approach 1:
The patent segments the DAC functionality into separate circuits for different voltage ranges. The first DAC circuit handles first input voltages within the first voltage range, and the second DAC circuit handles second input voltages within the second voltage range. Each DAC circuit uses MOSFETs optimized for its specific voltage range, reducing the total MOSFET count and area while managing complexity through functional separation.
Solution Approach 2:
The patent creates a multi-functional system where the DAC device can handle both high-voltage and low-voltage conversion by selecting appropriate DAC circuits. The control circuit determines which DAC circuit to use based on the input signal characteristics, providing universal functionality across different voltage ranges while optimizing resource usage and reducing overall circuit complexity.
Data Source
AI summary
A DAC device includes a first DAC circuit and a second DAC circuit. The first DAC circuit includes multiple DAC portions, each of which includes multiple pMOSFETs. The second DAC circuit includes multiple DAC portions, each of which includes multiple nMOSFETs. For each of the first and second DAC circuits, bulk terminals of at least some of the MOSFETs of each DAC portion are for receiving a respective one of bulk voltages with different magnitudes, a gate terminal of each of the MOSFETs of the DAC portions is for receiving a gate signal, and voltage magnitudes of at least some of the gate signals received by each DAC portion switch between a respective one of different logic high levels and a respective one of different logic low levels.