VCO-Based Pipelined ADC for Quantizer Error Cancellation

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Solution Overview

Problem

Existing analog-to-digital converters (ADCs) face challenges in high silicon area usage, power consumption, and achieving sufficient signal-to-noise ratio (SNR) and conversion bandwidth, especially in low voltage and low power deep submicron processes, due to limitations in Delta-Sigma ADC methods and VCO quantizer non-linearity.

Innovation Solution

A cascaded VCO-Based Delta-Sigma ADC is implemented, combining a VCO-Based Delta-Sigma ADC loop with a forward path quantizer to cancel VCO quantizer nonlinearity, utilizing a digital filter with a noise transfer function matching the noise transfer function of the first digital signal to remove harmonic distortion and achieve improved SNR and bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If VCO quantizer is used in Delta-Sigma ADC, then conversion bandwidth is improved, but non-linearity and harmonic distortion increase

Engineering Contradiction:

Improveconversion bandwidthVSAvoidquantizer linearity

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the output of the VCO quantizer is fed back through a digital filter with noise transfer function matching to cancel the non-linearity and harmonic distortion, allowing the VCO quantizer to operate at high bandwidth while maintaining linearity through active correction

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces a digital filter with noise transfer function matching as an intermediary component between the VCO quantizer and the final output. This intermediary processes the quantizer output to remove harmonic distortion while preserving the high conversion bandwidth benefit

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If higher order loop filter is used to suppress harmonic distortion, then SNR is improved, but power consumption and instability increase

Engineering Contradiction:

Improvesignal-to-noise ratioVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent changes the approach from using higher order loop filters to matching the noise transfer function of the digital filter with that of the VCO quantizer. This parameter change allows achieving the same SNR improvement with lower power consumption by operating at optimal filter order

Inventive Principle:

Principle #35Parameter changes

3Stability of the object's composition

If traditional ADC architectures are used, then stability is maintained, but silicon area and power consumption increase

Engineering Contradiction:

Improvesystem stabilityVSAvoidsilicon area

Core Design Contradiction:

Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

The patent segments the ADC functionality into a VCO-based quantizer stage and a separate digital filtering stage. This segmentation allows the use of a simpler, smaller VCO quantizer followed by a compact digital filter, reducing overall silicon area while maintaining stability through the structured architecture

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces traditional analog filtering mechanisms with digital filtering. By substituting analog components with digital logic, the system achieves reduced silicon area and power consumption while maintaining system stability through the deterministic nature of digital operations

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10931299B1Analog to digital converter with VCO-based and pipelined quantizers

Publication Date: 2021.02.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.