Split-Gate Laddered-Inverter Quantizer for Low-Power Fast-Settling ADCs
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) consume significant power and have slow settling speeds due to their quantizer circuits, particularly in multi-bit implementations, and are affected by process, voltage, and temperature (PVT) variations.
Innovation Solution
The implementation of a split-gate laddered-inverter quantizer, where an analog input and reference voltage are separately coupled to PMOS and NMOS gates via capacitances during clock phases, allowing independent bias voltage control to optimize current flow and settling speed, reducing power consumption and PVT variation impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a flash ADC quantizer is used, then quantization accuracy is achieved, but power consumption increases significantly
Solution Approach 1:
The quantizer is divided into multiple stages with different resolution levels. Coarse quantization is performed first with fewer comparators, followed by fine quantization only for the relevant range, reducing the total number of comparators from 2^m-1 to a much smaller number while maintaining overall accuracy
Solution Approach 2:
The quantizer operates in different modes depending on the input signal characteristics. The circuit dynamically switches between coarse and fine quantization modes, activating only the necessary comparators based on the signal range, thereby reducing average power consumption
2Use of energy by moving object
If a non-uniform quantizer is used, then power consumption is reduced, but settling speed becomes slow
Solution Approach 1:
The quantization process is segmented into coarse and fine stages. The coarse stage quickly establishes the basic range with fast settling, while the fine stage refines the measurement only within that established range, achieving both power efficiency and adequate settling speed
Solution Approach 2:
The coarse quantization stage performs preliminary action by quickly determining the signal range and activating only the necessary fine quantization comparators. This preliminary classification enables the fine stage to settle faster since it only needs to resolve a smaller voltage range
3Ease of operation
If conventional quantizer circuits are used, then quantization function is provided, but current consumption varies excessively with PVT changes
Solution Approach 1:
The quantizer incorporates feedback mechanisms that monitor the operating conditions and adjust the activation of comparators and reference voltages accordingly. This feedback control stabilizes current consumption across PVT variations by adapting the quantizer's operational mode to match actual circuit conditions
Solution Approach 2:
The circuit dynamically changes operating parameters such as comparator enable signals and reference voltage selections based on detected PVT conditions. By adjusting these parameters in response to environmental changes, the quantizer maintains stable current consumption while continuing to perform accurate quantization
Data Source
AI summary
An analog-to-digital converter (ADC) with split-gate laddered-inverter quantizer is presented herein. The ADC converts, via the split-gate laddered-inverter quantizer, an analog input voltage into a digital output value. The split-gate laddered-inverter quantizer separately couples, during respective phases of a clock signal via respective capacitances, a reference voltage and an input voltage corresponding to the analog input voltage to P-type metal-oxide-semiconductor (PMOS) gates of a PMOS branch of the split-gate laddered-inverter quantizer and N-type metal-oxide-semiconductor (NMOS) gates of an NMOS branch of the split-gate laddered-inverter quantizer to optimize current flow at respective frequencies. Further, the split-gate laddered-inverter quantizer separately biases, during the respective phases of the clock signal, the NMOS gates and the PMOS gates at respective bias voltages to optimize the current flow at the respective frequencies.