Shared Sample-and-Hold Integrator for Compact Delta-Sigma ADCs
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Solution Overview
Problem
Delta-sigma analog-to-digital converters (ADCs) face challenges due to the large area occupied by the sample-and-hold circuit on the ADC chip, which affects the overall efficiency and compactness of the device.
Innovation Solution
The delta-sigma ADC design incorporates a sample-and-hold circuit and an integrator that share a capacitor and an amplifier, utilizing switches and capacitors to efficiently sample and hold analog signals, allowing for a more compact and efficient conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate sample-and-hold circuit is implemented in a delta-sigma ADC, then the sampling and holding functions are performed effectively, but the chip area occupied increases significantly
Solution Approach 1:
The patent combines the sample-and-hold circuit and integrator into a single integrated structure where the first capacitor and amplifier are shared between both functions. The sample-and-hold circuit uses the first capacitor to store the sampled voltage, while the integrator simultaneously uses the same capacitor for integration operations, eliminating the need for separate dedicated components and reducing overall chip area.
Solution Approach 2:
The first capacitor and amplifier serve multiple functions: they act as the holding element for the sample-and-hold circuit during the sampling phase, and then serve as the integrating element for the integrator during the integration phase. This multi-functionality allows a single component to replace what would traditionally require separate dedicated components, thereby reducing the total chip area while maintaining effective signal conversion.
Data Source
AI summary
Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.